Test apparatus and test method

Details Test apparatus and test method Test apparatus and test method

2005-11-30

2008-11-04

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S005110, C714S025000, C714S719000, C714S720000, C714S723000, C714S734000, C714S736000, C714S742000, C714S746000, C714S819000, C365S200000, C365S201000

Reexamination Certificate

active

07447955

ABSTRACT:
There is provided a test apparatus for testing a memory-under-test for storing data strings to which an error correcting code has been added, having a logical comparator for comparing each data contained in the data string read out of the memory-under-test with an expected value generated in advance, a data error counting section for counting a number of data inconsistent with the expected value, a plurality of registers, provided corresponding to each of a plurality of classes, for storing an upper limit value of a number of errors contained in the data -under-test to be classified into the class, comparing sections for comparing each of the plurality of upper limit values stored in the plurality of registers with the counted value of the data error counting section and a classifying section for classifying the memory-under-test into the class corresponding to the register storing the upper limit value which is greater than the counted value.

REFERENCES:
patent: 4939694 (1990-07-01), Eaton et al.
patent: 7096397 (2006-08-01), Kundu et al.
patent: 2002/0104045 (2002-08-01), Cooper
patent: 2004/0223358 (2004-11-01), Yamamoto
patent: 2005/0047229 (2005-03-01), Nadeau-Dostie et al.
A High Density NAND Flash Memory Technology for a Silicon Movie Era Author: K. Sakui of Toshiba Corporation Semiconductor Company as Published in FED, vol. 11, No. 3 (2000) pp. 76-88.
International Search Report and Written Opinion of the Searching Authority for International Application No. PCT/JP2006/323527, mailed Feb. 15, 2007, 9 pages.

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