Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-03-20
2010-06-22
Ellis, Kevin L (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
07743305
ABSTRACT:
A test apparatus that tests a device under test is provided. The test apparatus includes: a main memory that stores a test data row for testing the device under test; a cache memory that caches the test data row read from the main memory; a pattern generation control section that reads each test data which is not aligned in units of word being a data transfer unit of the main memory and writes the same to cache entries different from each other in the cache memory for each test data; and a pattern generating section that sequentially reads the test data stored of each cache entry in the cache memory and generates a test pattern for testing the device under test.
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Office Action issued in German Application No. 10 2008 016 117.9-35 mailed on Nov. 9, 2009 and English translation thereof, 15 pages.
Advantest Corporation
Ellis Kevin L
Merant Guerrier
Osha • Liang LLP
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