Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-04-09
2009-10-13
Ellis, Kevin L (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S743000
Reexamination Certificate
active
07603604
ABSTRACT:
A test apparatus that tests a device under test is provided. The test apparatus includes: a pattern memory that stores in a compression format a test instruction sequence to define a test sequence for testing the device under test; an expanding section mat expands in a non-compression format the test instruction sequence read from the pattern memory; an instruction cache that caches the test instruction sequence which is expanded by the expanding section; a pattern generating section that sequentially reads instructions stored in the instruction cache and executes the same to generate a test pattern for the executed instruction; and a signal output section that generate a test signal based on the test pattern and provides the same to the device under test.
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Murata Kiyoshi
Yamada Tatsuya
Advantest Corporation
Ellis Kevin L
Nguyen Steve
Osha • Liang LLP
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