Test apparatus and electronic device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Details

C714S743000

Reexamination Certificate

active

07603604

ABSTRACT:
A test apparatus that tests a device under test is provided. The test apparatus includes: a pattern memory that stores in a compression format a test instruction sequence to define a test sequence for testing the device under test; an expanding section mat expands in a non-compression format the test instruction sequence read from the pattern memory; an instruction cache that caches the test instruction sequence which is expanded by the expanding section; a pattern generating section that sequentially reads instructions stored in the instruction cache and executes the same to generate a test pattern for the executed instruction; and a signal output section that generate a test signal based on the test pattern and provides the same to the device under test.

REFERENCES:
patent: 5737512 (1998-04-01), Proudfoot et al.
patent: 6769083 (2004-07-01), Tsuto et al.
patent: 0269685 (1990-03-01), None
patent: 0742150 (1995-02-01), None
patent: 200040389 (2000-02-01), None
patent: 2000162287 (2000-06-01), None
patent: 2000-206210 (2000-07-01), None
patent: 2002521698 (2002-07-01), None
patent: 200328936 (2003-01-01), None

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