Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-11-20
2007-11-20
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S736000
Reexamination Certificate
active
11311065
ABSTRACT:
There is provided a test having a pattern generating section for generating a test pattern, an expected value generating section for generating an expected value, an inversion cycle generating section for generating an expected value pattern of an output signal in which bits in a cycle of the expected value pattern in the output data corresponding to the cycle in which the electronic device outputs the data by inverting the bits thereof, an H-level judging section for outputting H fail data per bit of the expected value pattern of the output signal, a L-level judging section for outputting L fail data per bit of the expected value pattern of the output signal, a fail memory and selecting sections for switching a logic value of the H fail data and a logic value of the L fail data when the inversion cycle generating section inverts the bits of the expected value pattern.
REFERENCES:
patent: 5590137 (1996-12-01), Yamashita
patent: 6513138 (2003-01-01), Ohsawa
patent: 56-127253 (1981-10-01), None
patent: 02245675 (1990-10-01), None
patent: 0434299 (1992-12-01), None
patent: 9-293395 (1997-11-01), None
patent: 2001-133516 (2001-05-01), None
NN8803116 Array Test Pattern Generation Algorithms for a Per Pin TesterVolume No. 30 Issue No. 10 p. No. 116-123 Publication-Date Mar. 1, 1988 (19880301)□□.
International Search Report issued for PCT application No. PCT/JP2004/008228 mailed on Sep. 14, 2004, 1 page.
Advantest Corporation
Britt Cynthia
Osha & Liang LLP
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