Temporary self-aligned stop layer is applied on silicon...

Details Temporary self-aligned stop layer is applied on silicon... Temporary self-aligned stop layer is applied on silicon...

2005-12-06

2005-12-06

Coleman, W. David (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S184000, C438S199000, C438S224000, C438S225000, C438S231000, C438S301000, C438S558000, C257S336000, C257S374000, C257S408000, C257S900000

Reexamination Certificate

active

06972222

ABSTRACT:
A method is provided for forming NMOS and PMOS transistors with ultra shallow source/drain regions having high dopant concentrations. First sidewall spacers and nitride spacers are sequentially formed on the sides of a gate electrode followed by forming a self-aligned oxide etch stop layer. The nitride spacer is removed and an amorphous silicon layer is deposited. The etch stop layer enables a controlled etch of the amorphous silicon layer to form silicon sidewalls on the first sidewall spacers. Implant steps are followed by an RTA to activate shallow and deep S/D regions. The etch stop layer maintains a high dopant concentration in deep S/D regions. After the etch stop is removed and a titanium layer is deposited on the substrate, an RTA forms a titanium silicide layer on the gate electrode and an extended silicide layer over the silicon sidewalls and substrate which results in a low resistivity.

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