Temporary interconnect for semiconductor devices

Details Temporary interconnect for semiconductor devices Temporary interconnect for semiconductor devices

1999-03-30

2001-03-27

Saadat, Mahshid (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S738000, C257S778000, C257S772000

Reexamination Certificate

active

06208027

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to interconnection devices, and in particular, to a temporary interconnect for a semiconductor device to be connected with a package.
BACKGROUND OF THE INVENTION
The demand for semiconductor chip packages having high lead counts and small footprints has increased. In response to this increase in demand, semiconductor manufacturers have developed ball grid arrays, flip-chip, and chip scale technology. These semiconductor devices do not use traditional wire bonds to mount the devices to a package, rather they are mounted to a package using an array of solder balls or similar electrode bumps. These semiconductor devices with electrode bumps are generally mounted to the packages with the assistance of small pads or traces that are located on the packages. Once the semiconductor devices are properly aligned and fit together, the devices are heated in a furnace that causes the electrode bumps and the traces to fuse together, thereby creating a permanent electrical connection.
A typical ball grid array or pin grid array package contains a semiconductor chip that is connected with a substrate and the semiconductor chip is wire bonded to electrical traces in the substrate. To create the complete package, the semiconductor chip is generally encapsulated with a mold material or sealed with a metal lid and the electrode bumps are bonded to the electrical traces on the bottom surface of the substrate. In a flip-chip package, the solder bumps are attached directly to the electrical traces formed in the surface of the chip. The flip-chip devices are underfilled with an underfill material to increase their reliability, but are not generally encapsulated by a molded material. Thus, flip-chip packages are extremely fragile and must be handled with great care.
A chip scale package is a combination of ball grid array packages and of flip-chip packages. A chip scale package has electrode bumps that are attached directly to electrical traces on the surface of the chip. The electrode bumps can also be attached directly to the bond pads through openings in the encapsulating material. The electrical traces connect the external electrode bumps directly to the bond pads in the chip, thereby reducing the size of the overall semiconductor chip.
The present devices and methods of interconnecting a semiconductor chip with a package include the use of some form of electrode bumps and traces. As previously stated, in practice, the semiconductor chip is attached to the package by reflowing the package together with the semiconductor chip in a furnace. A metallurgical bond forms between the semiconductor bumps and the package traces creating the desired electrical connection. In general, the furnace heats the devices to a predetermined point where the electrode bumps and package traces fuse together thereby making a permanent electrical connection.
The problem with these prior art devices and methods of connecting semiconductor chips with packages is that the traces that are used on the package and the electrode bumps of the semiconductor must be physically bonded together. As previously discussed, the devices are physically bonded together by heating the two components to the melting point of the electrode bumps and package traces. Often, designers, product engineers, or wafer process engineers want to remove the semiconductor chip from the package after they have been interconnected for failure or performance analysis. Other times, product engineers may want to evaluate different packages for performance using the same semiconductor chip. Removing the semiconductor chip from the package is extremely difficult without damaging the semiconductor chip because the electrode bumps and the package traces have been fused together during the assembly process. As such, a need exists for a temporary interconnect device or bump nest that allows easy temporary attachment and removal of semiconductor chips from package traces without having to fuse the respective interconnection devices together.
BRIEF SUMMARY OF THE INVENTION
The present invention discloses temporary interconnection methods and devices that allows the semiconductor chip to be temporarily connected with the package without having to be fused together. As such, the electrode bumps of the semiconductor chip can easily be removed from the package for analysis without damaging the semiconductor chip. In preferred embodiments, the temporary interconnect is made of gold; however, one skilled in the art would recognize that any highly conductive material may be used, such as aluminum or copper. The disclosed temporary interconnection device can be used in a wide variety of applications in the electronic industry.
The disclosed temporary interconnect includes a contact group comprising a plurality of contact elements, spaced to provide at lease one conductive interfaces with an electrode bump of a semiconductor chip. Each of the contact elements can include an encircling contact pad and a projecting contact guide. In the preferred embodiment, the contact elements are concentrically located on a base pad. The projecting contact guides and the encircling contact are spaced in a manner on the base pad so as to surround the electrode bump of the semiconductor chip and provide an electrical connection with the package.


REFERENCES:
patent: 5457879 (1995-10-01), Gurtler et al.
patent: 5929521 (1999-07-01), Wark et al.

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