TEG pattern for detecting void in device isolation layer and...

Details TEG pattern for detecting void in device isolation layer and... TEG pattern for detecting void in device isolation layer and...

2011-07-05

2011-07-05

Dang, Trung (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

C257SE23179

Reexamination Certificate

active

07973309

ABSTRACT:
Provided is a test element group (TEG) pattern for detecting a void in a device isolation layer. The TEG pattern includes active regions which are parallel to each other and extend in a first direction, a device isolation layer that separates the active regions, a first contact that is formed across the device isolation layer and a first one of the active regions that contacts a surface of the device isolation layer, and a second contact that is formed across the device isolation layer and a second one of the active regions that contacts another surface of the device isolation layer.

REFERENCES:
patent: 7098049 (2006-08-01), Hsu et al.
patent: 7416986 (2008-08-01), Zhu et al.
patent: 2005/0104063 (2005-05-01), Hsu et al.
patent: 2007-123755 (2007-05-01), None
patent: 10-2005-0067766 (2005-07-01), None
patent: 10-2006-0078920 (2006-07-01), None

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