Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
1999-07-22
2001-06-12
Le, Vu A. (Department: 2824)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S026000, C438S127000, C438S106000, C228S180220
Reexamination Certificate
active
06245595
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to flip chip packaging for integrated circuits. More particularly, it relates to flip chips that have an integral layer of underfill material and to methods for and devices for packaging such flip chips.
BACKGROUND OF THE INVENTION
There are a number of conventional processes for packaging integrated circuits. One approach which is commonly referred to as “flip chip” packaging generally contemplates forming solder bumps (or other suitable contacts) directly on I/O pads formed on an integrated circuit die. The die is then typically attached to a substrate such as printed circuit board or package substrate such that the die contacts directly connect to corresponding contacts on the substrate. That is, the die is placed on the substrate with the contact bumps facing corresponding contacts on the substrate. The solder contact bumps are then reflowed to electrically connect the die to the substrate.
When a flip chip is attached to the substrate, an air gap typically remains between flip chip and substrate. This gap is commonly filled with material that is flowed into the gap in liquid form and is then solidified. This material is generally a mixture of a resin and small silica spheres and is generally called underfill. The underfill material is typically applied in liquid form from a dispenser at one edge of a flip chip. The material then flows into the narrow gap and spreads across the flip chip until finally the entire area of the gap between flip chip and substrate is filled.
There are problems associated with underfill. For example, the operation of applying underfill must be repeated for each flip chip. Repeating such an operation many times adds to the cost of manufacture. Also, as the underfill material flows past solder bumps to fill the gap, separation of glass from resin may occur. The separation of silica spheres from the resin occurs as some silica spheres become trapped as they meet solder ball obstacles. The underfill material will develop streaks of high and low silica concentration. The silica may also separate from the resin by sinking to one side of the gap, thus creating a silica rich side and a resin rich side. This segregation of silica and resin alters the mechanical properties of the filled region and thereby negates the mechanical function of the underfill.
Therefore there is a need for a lower cost underfill application process and there is a need to reduce the amount of silica segregation that occurs.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects and in accordance with the purpose of the present invention, methods for forming a layer of underfill encapsulant on an integrated circuit are disclosed. In one embodiment, the integrated circuit has electrically conductive pads, selected ones of which have a corresponding bonded solder ball. The solder balls are flattened which has the effect of increasing the available solder wetting area. The layer of underfill encapsulant is then formed by, in one embodiment, injecting underfill encapsulant under pressure onto the integrated circuit. In this way, the flattened solder ball is covered by the encapsulant in such a way that the flattened portion is substantially free of encapsulant. After the layer of underfill encapsulant is formed, it is partially, or pre-cured.
The integrated circuit can be one of a plurality of integrated circuits that populate an active surface of a wafer. In a preferred embodiment, some of the integrated circuits are flip chip integrated circuits.
In another embodiment, a flip chip integrated circuit package is disclosed. The flip chip integrated circuit package includes a substrate having a plurality of substrate bond pads suitable for being electrically coupled to external circuitry. The flip chip integrated circuit package also includes a flip chip integrated circuit having flip chip bond pads. All of the flip chip bond pads have flattened solder balls. The flattened solder balls have correspondingly enlarged wetting areas that are directly aligned to and in direct contact with corresponding substrate bond pads. A substantially uniform layer of underfill encapsulant that is fully cured during a solder reflow is juxtaposed between the substrate and the flip chip integrated circuit.
In yet another embodiment, an apparatus for forming a layer of underfill encapsulant on an integrated circuit having electrically conductive pads is disclosed. The apparatus flattens the solder balls associated with the selected pads as well as forms the layer of underfill adhesive providing for the flattened portion of the solder balls to remain substantially free of underfill encapsulant. The apparatus partially cures the layer of underfill encapsulant.
In still another embodiment of the invention, a method for forming a layer of underfill encapsulant on an integrated circuit having electrically conductive pads some of which have bonded solder balls is described. A portion of selected ones of the solder balls is flattened. The layer of underfill encapsulant is formed on the active surface of the integrated circuit such that the flattened portion of most of the solder balls remains substantially free of encapsulant. The layer of underfill encapsulant is then partially cured.
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Mostafazadeh Shahram
Nguyen Luu
Smith Joseph O.
Takiar Hem P.
Warner Ethan
Beyer Weaver & Thomas LLP
Le Vu A.
National Semiconductor Corporation
Pyonin Adam
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