Techniques for triple and quadruple damascene fabrication

Details Techniques for triple and quadruple damascene fabrication Techniques for triple and quadruple damascene fabrication

1998-10-01

2001-05-01

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000, C438S638000, C438S666000, C438S700000, C438S738000, C438S740000

Reexamination Certificate

active

06225207

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor device interconnect lines and via plugs which are fabricated using damascene techniques.
BACKGROUND OF THE INVENTION
A semiconductor device such as an IC (integrated circuit) generally has electronic circuit elements such as transistors, diodes and resistors fabricated integrally on a single body of semiconductor material. The various circuit elements are connected through conductive connectors to form a complete circuit which can contain millions of individual circuit elements. Advances in semiconductor materials and processing techniques have resulted in reducing the overall size of the IC circuit elements while increasing their number on a single body. Additional miniaturization is highly desirable for improved IC performance and cost reduction. Interconnects provide the electrical connections between the various electronic elements of an IC and they form the connections between these elements and the device's external contact elements, such as pins, for connecting the IC to other circuits. Typically, interconnect lines form horizontal connections between electronic circuit elements while conductive via plugs form vertical connections between the electronic circuit elements, resulting in layered connections.
A variety of techniques are employed to create interconnect lines and via plugs. One such technique involves a process generally referred to as dual damascene, which includes forming a trench and an underlying via hole. The trench and the via hole are simultaneously filled with a conductor material, for example a metal, thus simultaneously forming an interconnect line and an underlying via plug. Examples of conventional dual damascene fabrication techniques are disclosed in Kaanta et al., “Dual Damascene: A ULSI Wiring Technology”, Jun. 11-12, 1991, VMIC Conference, IEEE, pages 144-152 and in U.S. Pat. No. 5,635,423 to Huang et al., 1997.
An example of a prior art dual damascene technique is illustrated in
FIGS. 1A-1C
, showing various IC structures. As depicted in
FIG. 1A
, a dielectric layer
110
is deposited on a semiconductor substrate
112
. An etch mask
116
, having a via pattern
118
, is positioned on dielectric layer
110
. A timed anisotropic etch is utilized to etch a hole
120
in layer
110
conforming to the via pattern. Mask
116
is subsequently replaced by mask
122
(
FIG. 1B
) having a trench pattern
124
. A timed anisotropic etch is used to form trench
126
and to simultaneously deepen hole
120
to form via hole
128
. This via hole can be etched to expose semiconductor substrate
112
. Alternatively, the via hole can be over-etched partly into the substrate. As illustrated in
FIG. 1C
, the via hole and trench are then filled simultaneously with a suitable metal
130
. Metal
130
thus forms a metallized interconnect line
132
and a via plug
134
which is in contact with semiconductor substrate
112
. Additionally, a liner or barrier layer may be deposited inside the via hole and the trench prior to deposition of the interconnect metal and the via plug. The surface of layer
110
is planarized to remove excess metal
130
and to define interconnect line
132
. Alternately, metal etch-back can be utilized to define the line.
Another example of prior art dual damascene is shown in IC structures illustrated in
FIGS. 2A-2C
. As depicted in
FIG. 2A
, a first dielectric layer
210
is deposited on a semiconductor substrate
212
. An etch stop layer
216
, is deposited on first dielectric layer
210
. A second dielectric layer
218
is deposited on etch stop
216
, and an etch mask
220
is positioned on dielectric layer
218
. Etch mask
220
is patterned (
221
) for etching a via hole. Second dielectric layer
218
is etched using a first anisotropic etch procedure, to form a hole
222
(
FIG. 2A
) conforming to the via pattern. This etching procedure is stopped at etch stop layer
216
. Etch mask
220
is removed and another etch mask
224
(see,
FIG. 2B
) is positioned on second dielectric layer
218
such that it is patterned (
226
) for forming a trench. A second anisotropic etch procedure is used to etch trench
228
in layer
218
. Simultaneously, hole
222
is extended to substrate
212
, by etching through etch stop layer
216
and through first dielectric layer
210
. In this dual damascene technique the first etch procedure has a greater selectivity to etch stop layer
216
than the second etch procedure. As shown in
FIG. 2B
, the second etch procedure results in forming trench
228
and via hole
230
which extends to semiconductor substrate
212
. Mask
224
is removed, after which trench
228
and via hole
230
are simultaneously filled with a suitable conductive metal
232
(see,
FIG. 2C
) forming metallized line
234
and via plug
236
which contacts substrate
212
. Excess metal
232
is removed from the surface of layer
218
to define line
234
.
Conventional dual damascene techniques, such as those exemplified above, have shortcomings for fabricating structures which include power interconnect lines as well as signal interconnect lines. Power lines, which are fabricated for conducting a relatively high current, generally have a greater thickness and pitch than signal lines. Consequently, power lines typically extend through more dielectric layers or interconnect levels than signal lines which are fabricated in the same structure. One conventional technique for fabricating a structure including a power line and a signal having an underlying via plug includes etching the signal line trench to the same depth as the power line trench. Subsequently, both trenches and the underlying via holes are simultaneously filled with a conductive material. This results in a deep and narrow signal line which is difficult to fill reliably with metal. Also, such a deep and narrow signal line results in an undesirable increase in intermetal capacitance. In another conventional technique, the power line and signal line with an underlying via plug are fabricated in different interconnect levels, thereby requiring one or more additional interconnect levels, additional metal fill processing steps and one or more additional mask layers, in order to meet the different design rule requirements regarding line pitch and thickness for power lines and signal lines. This latter technique is not suitable for simultaneously filling a power line trench and a signal line trench of a damascene structure with a conductive material because these different trenches are not accessible for filling with metal at the same interconnect level.
Accordingly, a need exists for cost effective, improved techniques for damascene fabrication, wherein a power line and a signal line are simultaneously formed.
SUMMARY OF THE INVENTION
The present invention provides novel methods and structures for damascene containing integrated circuit devices which overcome the prior art problems described above.
In one embodiment of the present invention, a first dielectric layer is deposited on a substrate, such as a semiconductor substrate. Subsequently, second, third, fourth and fifth dielectric layers are deposited. The first and fifth dielectric layers have similar etching characteristics, i.e. the layers are capable of being etched at similar etching rates in a particular etch chemistry. Also, the first, third and fifth dielectric layers have etching characteristics which are dissimilar from those of the second and fourth dielectric layers, i.e. the etching properties of these materials are such that first, third and fifth dielectric layers etch at a different rate than the second and fourth dielectric layers in a specific etch chemistry. A first etch mask, patterned for a power line trench and a via, is formed on the fifth dielectric layer. A first etching sequence is used to simultaneously anisotropically etch the power line trench pattern and the via pattern through the fifth, fourth and third dielectric layers. The second dielectric layer is an etch stop for the first etching sequence. The first etch mask

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