Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2011-07-19
2011-07-19
Ton, David (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S030000, C714S726000
Reexamination Certificate
active
07984344
ABSTRACT:
An integrated circuit includes a memory circuit, a read address register coupled to a read address port of the memory circuit, a write address register coupled to a write address port of the memory circuit, and a multiplexer configurable to transmit a read address bit from the write address register to the read address register in response to a read control signal. The read address register loads the read address bit into the memory circuit through the read address port during a test of the memory circuit. The integrated circuit may include a multiplexer configurable to transmit a write address bit from the read address register to the write address register in response to a write control signal. The write address register loads the write address bit into the memory circuit through the write address port during the test of the memory circuit.
REFERENCES:
patent: 4888741 (1989-12-01), Malinowski
patent: 5115411 (1992-05-01), Kass et al.
patent: 5303200 (1994-04-01), Elrod et al.
patent: 5910928 (1999-06-01), Joffe
patent: 5917832 (1999-06-01), Baeg et al.
patent: 6170046 (2001-01-01), Joffe et al.
patent: 6310875 (2001-10-01), Nichols et al.
patent: 6370617 (2002-04-01), Lu et al.
patent: 6449740 (2002-09-01), Yoshie
patent: 6492833 (2002-12-01), Asson et al.
patent: 6545937 (2003-04-01), Pawlowski
patent: 6680871 (2004-01-01), Prince
patent: 6829728 (2004-12-01), Cheng et al.
patent: 7000165 (2006-02-01), Asson et al.
patent: 7055075 (2006-05-01), Koss et al.
patent: 7057962 (2006-06-01), Tan et al.
patent: 7257751 (2007-08-01), Stong et al.
patent: 7266028 (2007-09-01), Ghosh Dastidar
patent: 7665003 (2010-02-01), Shen et al.
Ang Chin Hai
Ismail Ala-Uddin
Tan Tze Sin
Yeoh Siew Ling
Altera Corporation
Cahill Steven J.
Ton David
LandOfFree
Techniques for testing memory circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Techniques for testing memory circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Techniques for testing memory circuits will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2720742