Techniques for packaging multiple device components

Details Techniques for packaging multiple device components Techniques for packaging multiple device components

2005-02-15

2005-02-15

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S777000

Reexamination Certificate

active

06856009

ABSTRACT:
Techniques for fabricating multiple device components. Specifically, techniques for fabricating a stacked package comprising at least one I/C module and a multi-chip package. The multi-chip package includes a plurality of integrated circuit dices coupled to a carrier. The dice are encapsulated such that conductive elements are exposed through the encapsulant. The conductive elements are electrically coupled to the chips. The I/C module comprises an interposer having a plurality of integrated circuit dice disposed thereon. The dice of the I/C module are electrically coupled to the interposer via bondwires. The interposer is configured such that vias are aligned with the conductive elements on the multi-chip package. The multi-chip package and I/C module may be fabricated separately and subsequently coupled together to form a stacked package.

REFERENCES:
patent: 5903049 (1999-05-01), Mori
patent: 6583502 (2003-06-01), Lee et al.
patent: 6762488 (2004-07-01), Maeda et al.

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