Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2004-12-13
2008-10-07
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C710S305000, C710S315000, C710S020000, C370S516000, C370S503000, C375S364000, C375S365000, C326S026000, C326S041000, C326S047000
Reexamination Certificate
active
07434192
ABSTRACT:
Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.
REFERENCES:
patent: 4062699 (1977-12-01), Armstrong
patent: 4745564 (1988-05-01), Tennes et al.
patent: 5369624 (1994-11-01), Fukukita et al.
patent: 5576910 (1996-11-01), Romano et al.
patent: 5708436 (1998-01-01), Loiz et al.
patent: 5825202 (1998-10-01), Tavana et al.
patent: 5874834 (1999-02-01), New
patent: 5887039 (1999-03-01), Suemura et al.
patent: 6091262 (2000-07-01), New
patent: 6094065 (2000-07-01), Tavana et al.
patent: 6242945 (2001-06-01), New
patent: 6292116 (2001-09-01), Wang
patent: 6317804 (2001-11-01), Levy et al.
patent: 6490707 (2002-12-01), Baxter
patent: 6515509 (2003-02-01), Baxter
patent: 6526563 (2003-02-01), Baxter
patent: 6724328 (2004-04-01), Lui et al.
patent: 6744274 (2004-06-01), Arnold et al.
patent: 6874107 (2005-03-01), Lesea
patent: 7129859 (2006-10-01), Dreps et al.
patent: 2002/0089348 (2002-07-01), Langhammer
patent: 2003/0052709 (2003-03-01), Venkata et al.
patent: 2003/0065859 (2003-04-01), Dao et al.
patent: 2004/0032282 (2004-02-01), Lee et al.
patent: 2004/0156398 (2004-08-01), Abel et al.
patent: 2006/0033646 (2006-02-01), Dreps et al.
patent: 2006/0117275 (2006-06-01), Jones
patent: 2008/0107049 (2008-05-01), Stanwood et al.
patent: 1134668 (2001-09-01), None
“Atlantic Interface,” Altera Functional Specification 13, version 3.0, Altera Corporation San Jose, CA (Jun. 2002), pp. 1-10.
“FPGAs & FPSCs from Lattice: ORSP14,” product information from http://www.latticesemi.com, Lattice Semiconductor Corporation Hillsboro, OR (2003), pp. 1-64.
“ORCA® ORSPI4 Dual SPI4 Interface and High Speed Serdes FPSC,” product information Lattice Semiconductor Corporation Hillsboro, OR (2004), 3 pages.
System Packet Interface Level 4 (SPI-4) Phase 2: OC-192 System Interface for Physical and Link Layer Devices, Optical Internetworking Forum Implementation Agreement : OIF-SPI4-02.0 (Jan. 2001), pp. 1-243.
Ang Boon-Jin
Burney Ali
Chong Thow-Pang
Mansur Dan
van Wageningen Darren
Altera Corporation
Kik Phallaka
Townsend and Townsend / and Crew LLP
LandOfFree
Techniques for optimizing design of a hard intellectual... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Techniques for optimizing design of a hard intellectual..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Techniques for optimizing design of a hard intellectual... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4016714