Techniques for mapping functions to lookup tables on...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C716S030000, C716S030000

Reexamination Certificate

active

10694919

ABSTRACT:
Techniques for mapping functions in a user design to lookup tables on a programmable integrated circuit are provided. Functions within a user design are rewritten as a composition of smaller, decomposed functions using a decomposition technique. An attempt is made to fit the decomposed functions into a lookup table configuration. If the decomposed functions do not fit into one the lookup table configurations for the programmable integrated circuit, the input variables are rotated within the user function. Then, an attempt is made to decompose the user function again based on the rotated input variables.

REFERENCES:
patent: 5521835 (1996-05-01), Trimberger
patent: 6360352 (2002-03-01), Wallace
patent: 6480023 (2002-11-01), Kaviani
patent: 6603332 (2003-08-01), Kaviani et al.
patent: 2004/0133869 (2004-07-01), Sharma
patent: 2004/0155676 (2004-08-01), Kaptanoglu et al.
Valeria Bertacco & Maurizio Damiani, “The Disjunctive Decomposition of Logic Functions”, ICCD97, Nov. 1997, pp. 78-82, IEEE Computer Society, Los Alamitos, CA, USA.□□
Robert J. Francis, “A Tutorial on Logic Synthesis for Lookup-Table Based FPGAs”, pp. 40-47, 1992 IEEE.
Robert J. Francis et al., “Technology Mapping of Lookup Table-Based FPGAs for performance”, pp. 568-571, 1991 IEEE.
Vemuri et al., “BDD-Based Logic Synthesis for LUT-Based FPGAs”, ACM Transactions on Design Automation of Electronic systems, vol. 7, No. 4, Oct. 2002, pp. 501-525.
Cong, J and Ding, Y (1996). “Combinational logic synthesis for (LUT) based field programmable gate arrays,” ACM Trans. Des. Autom. Electron. Syst. 1(2):145-204.
Cong, J. and Hwang, Y. (2001). “Boolean Matching for LUT-Based Logic Blocks With Applications to Architecture Evaluation and Technology Mapping,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 20(9):1077-1090.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Techniques for mapping functions to lookup tables on... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Techniques for mapping functions to lookup tables on..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Techniques for mapping functions to lookup tables on... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3794926

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.