Techniques for improving write stability of memory with...

Details Techniques for improving write stability of memory with... Techniques for improving write stability of memory with...

2007-01-30

2009-02-24

Dinh, Son (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S194000

Reexamination Certificate

active

07495969

ABSTRACT:
In a memory circuit, data from all cells along a selected word line is read. Then, the read data is written back to half-selected cells and new data is written to the selected cells in the next cycle. In cases where a READ bit line (RBL) and WRITE bit line (WBL) are decoupled, RBL and WBL can be accessed simultaneously. Hence, the WRITE in the n-th cycle can be delayed to the n+1-th cycle as far as there is no data hazard such as reading data from memory before correct data are actually written to memory. As a result, there is no bandwidth loss, although the latency of the WRITE operation increases. WRITE stability issues in previous configurations with decoupled RBL and WBL are thus addressed.

REFERENCES:
patent: 6279144 (2001-08-01), Henkels et al.
patent: 7075811 (2006-07-01), Iwanari
patent: 7087942 (2006-08-01), Osada et al.
LeLand Chang et al., “Stable SRAM Cell Design for the 32 nm Node and Beyond”; 2005 VLSI Technology Symposium.

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