Technique to reduce reflections and ringing on CMOS...

Details Technique to reduce reflections and ringing on CMOS... Technique to reduce reflections and ringing on CMOS...

1999-08-30

2003-04-22

Le, Don (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S101000, C333S032000, C333S247000

Reexamination Certificate

active

06552564

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to interconnections within a computer, in particular, to a method and apparatus capable of minimizing reflections, ringing, and delay on long CMOS interconnections in an integrated circuit, between integrated circuits, and between integrated circuits and other circuits.
BACKGROUND OF THE INVENTION
Recent efforts in interconnections have revolved around minimizing the resistivity of the metals, in particular copper metallurgy for CMOS integrated circuits, used in interconnections. The problem is that minimizing the resistivity on long interconnection lines is not always the optimum solution when signal quality is also an important factor. The use of long interconnection lines where the resistivity is minimized may lead to problems with ringing and reflections on the line.
A typical long interconnection line, long being defined as an interconnection line of about 1 cm long or longer, would be a clock distribution line which is used to send clock signals to destination points within an integrated circuit or printed circuit board. Clock signal delay or skew, caused by the characteristics of the distribution line, is an important factor in the transmission of clock signals and for this reason many interconnection or distribution lines attempt to minimize resistivity. However, if signal quality at the destination point is important then consideration must also be given to minimize the reflections and ringing along the line.
FIG. 1
illustrates an interconnection which incorporates a signal source
5
which has an output impedance Zs, a long interconnection line
6
, and a destination point D
1
. The long interconnection line
6
has an overall impedance Zo shown as line resistance R
L
, inductance L
L
, and capacitance C
L
. The long interconnection line
6
begins at node N
2
and terminates at node N
3
. Connected to node N
3
is a termination line with a small capacitance C
S
and destination point D
1
.
Typically, only an interconnection line
6
with minimal resistivity would be used to reduce or minimize signal delay or skew. However, an interconnection line where the resistivity is minimized would lead to potential ringing and reflection problems, which ultimately detract from the quality of the signal received. The signal quality is typically not addressed by conventional interconnection line circuits.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by the invention which reduces reflections and ringing on CMOS interconnections by altering the geometry of the interconnection lines to obtain interconnection line characteristics which minimize reflections, ringing and delay.
Minimizing the resistivity on long interconnection lines may lead to problems with ringing and reflections on the line. As will be discussed in further detail below, the optimum choice for a long interconnection line is a line where the reflection signals at the source end N
2
are attenuated by a round trip transit over the length of the line. Although for signal delay purposes the minimization of line resistivity is favorable, making the line resistance larger can improve signal quality. Therefore interconnection line characteristics and the associated geometry of the interconnection lines are considered to obtain interconnection line characteristics which will insure proper signal attenuation and signal quality.
The foregoing and other features and advantages of the invention will be more clearly understood from the following detailed description of the invention which is provided in conjunction with the accompanying drawings.


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patent: 6046653 (2000-04-01), Yamada
patent: 6271678 (2001-08-01), Sochoux
Edelstein et al; “Full Cooper Wiring in a Sub-0.25 &mgr;m CMOS ULSI Technology”; Tech. Digest of 1997 IEDM; pp. 773-776.
Venkatesan et al.; “A High Performance 1.8V, 0.20 &mgr;m CMOS Technology with Copper Metallization”; Tech. Digest of 1997 IEDM; pp. 769-772.
Matsuura et al.; “A Highly Reliable Self-planarizing Low-k Internal Dielectric for Sub-quarter Micron Interconnects”; Tech. Digest of 1997 IEDM; pp. 785-788.
Aoki et al.; “A Degradation-Free Cu/HSQ Damascene Technology using Metal Mask Patterning and Post-CMP Cleaning by Electrolytic Ionized Water”; Tech. Digest of 1997 IEDM; pp. 777-781.
Rabaey; “Digital integrated Circuits”, A Design Perspective, Prentice Hall Electronics and VSLI Series 1996; pp. 482-493.

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