Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-03-15
2004-05-11
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06734510
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of semiconductor transistors that are scaled down to sub-micron sizes.
BACKGROUND OF THE INVENTION
There is ever-present pressure in the semiconductor industry to develop smaller and more highly integrated devices. As the industry standard approaches smaller and smaller scaled devices, problems with further advancement are presented and it becomes more difficult to produce sub-micron devices that can perform as desired.
As MOSFET are scaled to deep sub-micron dimensions it becomes increasingly difficult to maintain an acceptable aspect ratio, as shown in
FIG. 1
a
.
FIG. 1
a
shows a representational illustration of a MOSFET having a polysilicon gate
3
over a substrate
5
, with the two being separated by a gate oxide
7
. Source and drain regions
9
of the substrate are on either side of the gate structure, forming a transistor. The aspect ratio equation represents the spatial relationship between the elementary parts of a MOSFET device, specifically between the distance between the source/drain areas defining the effective gate length (L), the width of the depletion region (W
d
), the depths of the source/drain areas (x
j
), and the gate oxide thickness (t
ox
). Detrimental short-channel effects occur when the gate length (L) is reduced by the same order as the width of the depletion region (W
d
). In current trends, not only are the gate oxide thicknesses scaled to under 5 nm (50 Å) dimensions as the channel lengths are shortened to sub-micron sizes, but also, the depletion widths (synonymous with W
d
) and source/drain junction depths (x
j
) must be scaled to smaller dimensions as well. The depletion region width (or space charge) (W
d
) are made smaller by increasing the substrate or channel dopings. However, it is extremely difficult to scale junction depths to under 100 nm dimensions because these are doped by ion implantation and thermally activated.
Related to aspect ratio are short channel effects, which are highly dependent on the channel length. For shorter channel devices (channel lengths below 2 &mgr;m) a series of effects arise that result in deviations from the predictable performance of larger scaled devices. Short channel effects impact threshold voltage, subthreshold currents, and I-V behavior beyond threshold. Techniques have been developed for avoiding short channel effects in MOSFETs, such as the “straddle gate” transistor shown in
FIG. 1
b
. Such a structure utilizes thinner gate oxides
11
under the gate sidewall spacers
21
to allow the regions to turn-on easier and at lower voltages. A thicker gate oxide
15
is provided beneath the gate
17
. These thinner regions produce a “virtual” source/drain junction
19
with minimal junction depth. The problem with such structures is that gate oxides are already approaching theoretical minimal values, therefore, regions of even thinner gate oxides pose reliability risks. It would be beneficial to devise a semiconductor having an acceptable aspect ratio, where the channel length is large enough when the device is “off” to avoid short channel effects and undesired shorting of the device, and where the device channel is short enough when the device is “on” to allow for the fastest operation possible.
SUMMARY OF THE INVENTION
This invention relates to a process of forming a transistor having three adjacent gate electrodes and the resulting transistor. In forming such a transistor it is possible to mitigate short channel effects as MOSFET structures are scaled down to sub-micron sizes. This transistor fabrication process can utilize different materials for the gate electrodes so that the workfunctions of the three gate electrodes can be tailored to be different. The three gate electrodes can be connected by a single conducting line and all three are positioned over a single channel and operate as a single gate having a pair of outer gate regions and an inner gate region. This allows for use with higher source and drain voltages. These devices provide for higher performance, using a standard or scaled down transistor surface area, than can be achieved with conventional transistor structure. They have smaller effective channel lengths when “on,” and consequently, faster speeds are achievable. The devices have longer channel lengths when “off,” thereby mitigating short channel effects.
In an alternative arrangement the two side gate electrodes can be independently biased to a fixed voltage to turn on portions of the channel regions over source/drain extensions and the inner gate can subsequently turn on a portion of the channel region between the source/drain regions.
These and other features and advantages of the invention will be more clearly understood from the following detailed description of the invention which is provided in connection with the accompanying drawings.
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Ahn Kie Y.
Forbes Leonard
Tran Luan C.
Dickstein Shapiro Morin & Oshinsky
Flynn Nathan J.
Micron Technology, Ing.
Quinto Kevin
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