Technique to improve deep trench capacitance by increasing...

Details Technique to improve deep trench capacitance by increasing... Technique to improve deep trench capacitance by increasing...

2000-10-10

2002-12-17

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S243000, C438S700000, C438S701000, C438S386000, C438S238000, C438S255000, C438S398000, C438S665000, C438S964000, C257S301000, C257S309000

Reexamination Certificate

active

06495411

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for improving the capacitance of a deep trench capacitor formed into a silicon substrate as part of a semiconductor device by increasing the surface area inside the deep trench. More specifically, the present invention relates to a novel method for improving the capacitance of a vertically elongated trench, or deep trench, that is formed into a crystalline silicon substrate as part of a semiconductor device, such as a dynamic random access memory (DRAM) cell, by increasing its effective sidewall surface area. Unlike the bottle-shaped deep trenches, the method of the present invention does not need to enlarge the diameter of the bottom portion of the deep trench. Thus, the present invention can very effectively increase the capacitance of a deep trench without incurring substantially increased manufacturing cost. But more importantly, the method of the present invention can be used in conjunction with DRAM technologies down to 0.15 &mgr;m or below, where it becomes very difficult to further enlarge the diameter and form a bottle-shaped deep trench.
BACKGROUND OF THE INVENTION
In order to reduce production cost and increase performance, semiconductor manufacturers are facing constant pressures to reduce the physical dimensions of semiconductor devices while containing the manufacturing cost. For dynamic random access memory (DRAM) cells, their nominal physical dimensions have now shrunk to 0.15 &mgr;m or below (and the technology associated with making the 0.15 &mgr;m cells is called the 0.15 &mgr;m technology, etc.). This presents great challenges in many technical areas.
The task to provide high capacitance capacitors for the deep sub-micron features presents one of the most challenges. The capacitance of a capacitor is proportional to the total surface area between the two electrodes of the capacitor. As the physical dimension of the semiconductor devices is reduced, the surface area of a deep trench is also reduced. Indeed, due to its reduced physical dimension, and thus reduced storage capacitance, the deep trench has become a key limiting factor for further reducing the size of semiconductors. One way to increase the surface area of a deep trench, of course, is to make it deeper. However, currently, the depth-to-diameter aspect ratio of the deep trench is already running more than 40 to 1. The size of the deep trench opening shrinks proportionally to the feature size of technology. As the technology moves from 0.17 &mgr;m to 0.15 &mgr;m or lower, it presents a major challenge to the etching technology to further increase the aspect ratio.
In order to further increase the surface area, and thus the storage capacitance, of a deep trench, the so-called bottle-shaped deep trenches have been developed. U.S. Pat. No. 5,658,816 (hereinafter the '816 patent) discloses a method which involves the steps of (1) forming the top portion of the deep trench; (2) forming a nitride sidewall spacer in the top portion of the deep trench; (3) forming the bottom portion of the deep trench; (4) oxidizing the bottom portion of the deep trench; and (5) etching the oxidized bottom portion of the deep trench to enlarge the diameter thereof.
Because the method disclosed in the '816 patent is high impractical, other techniques have been developed to form bottle-shaped deep trenches. For example, in an article entitled “0.228 &mgr;m Trench Cell Technologies with Bottle-Shaped Capacitor for 1 Gbit DRAMs”, by T. Ozaki, et al,
IEDM
, 95, PP661-664 (1995), the authors disclosed a method to increase the diameter of a deep trench. The method disclosed therein includes the steps of: (1) forming an 80 nm collar oxide at the upper portion of the trench by the selective oxidation; (2) performing a capacitor process which includes oxidation mask removal, native oxide removal, etc., during which process the collar oxide thickness reduces to 50 nm; and (3) in-situ phosphorous doped polysilicon is deposited and phosphorous doping into the trench side wall at the capacitor portion (plate electrode) is performed by the furnace annealing technology. The collar oxide prevents phosphorous doping at the upper portion of the trench; it also makes the electrical isolation between the plate electrode and the transfer transistor. The poly-silicon is removed by chemical dry etching and the diameter of the trench under the collar oxide is enlarged at the same time. The authors reported that the trench diameter is enlarged by 30%, thus forming a “bottled-shaped” deep trench.
U.S. Pat. No. 5,849,638 (hereinafter the '638 patent) discloses a method to further enhance the sidewall surface area of a deep trench. The method disclosed in the '638 patent, the content thereof in incorporated herein by reference, includes the steps of: (1) opening a deep trench mask at an angle for the first trench; (2) etching a trench using RIBE (reactive ion beam etching) with the wafer oriented 1 to 16 degrees off axis with respect to the ion source; (3) opening the deep trench mask at an angle for the second trench; (4) etching the trench using RIBE with the wafer oriented 1 to 15 degrees in the opposite direction; (5) oxide collar formation; and (6) chemical down-stream etching (CDE) to isotropically increase the size of the trench. Steps (5) to (6) were taken from and are identical to the procedure disclosed by Ozaki et al, which included the steps of forming an oxide collar and etching the entire trench sidewall not covered by the oxide collar. As with the Ozaki et al technique, the method taught in the '638 patent may not provide enough precision in deep sub-micron applications.
In a co-pending application, Ser. No. 09/327,872, which is invented by the same inventor of the present invention and the content thereof is incorporated herein by reference, it is disclosed a further improved method for forming bottle-shaped trenches which comprises the steps of: (a) forming a deep trench into an active region of a substrate, the deep trench having a sidewall defining the trench inside the substrate; (b) forming a oxide filler layer which fills the deep trench; (c) etching the oxide filler layer to a predetermined depth, to reveal an upper portion of the sidewall above the predetermined depth; (d) forming a nitride sidewall spacer cover the upper portion of the sidewall; (e) etching away the oxide filler layer to reveal the lower portion of the sidewall; (f) using the sidewall spacer as a mask to either selectively etch away the lower portion of the sidewall or cause the lower portion of the sidewall to be subject to a chemical reaction so that the lower portion of the sidewall can be etched away and thus causing the trench width in the lower portion to be enlarged; and (g) removing the chemically altered lower portion of the sidewall if it is not already removed, to form a bottle-shaped deep trench having an enhanced sidewall surface at the lower portion.
The process disclosed in the '872 application substantially improves the precision and simplifies the process of forming bottle-shaped deep trenches. However, since the storage surface of the deep trench capacitor is only linearly proportional to the diameter of the deep trench, the bottom portion of the deep trench must be substantially enlarged to achieve the intended improvement. Such enlargement becomes very difficult for deep sub-micron DRAM technologies of 0.15 &mgr;m and below. Thus, a radically different approach other than the bottle-shaped configuration must be developed in an attempt to increase the capacitance of deep trench capacitors.
U.S. Pat. No. 6,025,225 (hereinafter the '225 patent) discloses a method wherein an amorphous silicon layer is formed on the sidewall and bottom surface of a deep trench, the amorphous silicon layer is then roughened using an etching solution which contains phosphoric acid (H
3
PO
4
) to increase the surface of the trench capacitor. This method is impractical in that it attempts to increase the surface area by first reducing the diameter (and thus reducing

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