Technique to assess timing delay by use of layout quality...

Details Technique to assess timing delay by use of layout quality... Technique to assess timing delay by use of layout quality...

2005-04-05

2005-04-05

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C713S401000

Reexamination Certificate

active

06877147

ABSTRACT:
In one embodiment, a computer readable medium comprises at least first instructions and second instructions. The first instructions, when executed, compute a first plurality of routes. Each route of the first plurality of routes corresponds to a respective net of a plurality of nets in an integrated circuit layout, and represents a theoretically optimal route of the respective net according to a graph theory based algorithm. The second instructions, when executed, compare each of the first plurality of routes to a corresponding route of a current plurality of routes, each of the current plurality of routes corresponding to the respective net of the plurality of nets and currently existing in the integrated circuit layout. A method is also contemplated.

REFERENCES:
patent: 5805861 (1998-09-01), Gilbert et al.
patent: 6751744 (2004-06-01), Allen et al.
patent: 20020049957 (2002-04-01), Hosono et al.
patent: 20030018947 (2003-01-01), Teig et al.
“Rectilinear Full Steiner Tree Generation,” Martin Zachariasen, Technical Report DIKU-TR-97/29, Dept. of Computer Science, Dec. 1997, 36 pages.
“Exact Algorithms for Plane Steiner Tree Problems: A Computational Study,” Warme, et al., Technical Report DIKU-TR-98/11, Dept. of Computer Science, Apr. 1998, 33 pages.
“A New Exact Algorithm for Rectilinear Steiner Trees,” David M. Warme, Apr. 27, 1997, 42 pages.
“Rectilinear Full Steiner Tree Generation,” Martin Zachariasen, Technical Report DIKU-TR-97/29, Dept. of Computer Science, Dec. 1997, 36 pages.
“Large Euclidean Steiner Minimum Trees in an Hour,” Winer and Zachariasen, Dept. of Computer Schience, University of Copenhagen, Oct. 4, 1996, 28 pages.
“Spanning Trees in Hypergraphs with Applications to Steiner Trees,” David M. Warme, A Dissertation Presented to the Faculty of the School of Engineering and Applied Science-University of Virginia, May 1996, 122 pages.
“GeoSteiner, Software for Computing Steiner Trees,” (http://www.diku.dk/geosteiner/) Mar. 20, 2001, 2 pages.
“Low-Degree Minimum Spanning Trees,” Robins and Salowe, Dept. of Computer Science, University of VA, Feb. 11, 1999, 19 pages.
“ARIES: A rearrangeable Inexpensive Edge-Based On-line Steiner Algorithm,” Bauer and Varma, Computer Engineering Dept., University of CA, Aug. 10, 1995, 37 pages.
“Interconnect Layout Optimization by Simultaneous Steiner Tree Construction and Buffer Insertion,” Okamoto and Cong, Dept. of Computer Science, University of CA, 1996, 6 pages.
“Preferred Direction Steiner Trees,” Yildiz and Madden, State University of NY at Binghamton, Computer Science Dept., 2001, 6 pages.
“OR-Notes,” J.E. Beasley, printed from web site on May 30k, 2002, 22 pages.
“Prim's Algorithm,” National Institute of Standards and Technology, Sep. 30, 1999, 1 page.
“Kruskal's Algorithm,” National Institute of Standards and Technology, Feb. 4, 2002, 1 page.

Affiliated with

Also associated with

Rating

Technique to assess timing delay by use of layout quality... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Technique to assess timing delay by use of layout quality..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Technique to assess timing delay by use of layout quality... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3401241