Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2002-01-11
2002-12-31
Nguyen, Viet Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Precharge
C365S205000
Reexamination Certificate
active
06501695
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for memory devices generally and, more particularly, to a method and/or architecture for equalized memory access times.
BACKGROUND OF THE INVENTION
In conventional memories with large row counts, a distributed RC effect in the bit lines creates variable read access times that depend upon the location of the bit cell being read relative to the sense amplifiers. Reading data stored in bit cells far from the sense amplifiers takes more time than reading data stored in bit cells close to the sense amplifiers. For non-self-timed type memories, the minimum read time is thus limited by the slowest, furthest row of bit cells from the sense amplifiers.
Referring to
FIG. 1
, a timing diagram of a read access in a conventional memory is shown. A waveform
10
represents a voltage of a precharge signal. A waveform
12
represents a voltage of a wordline signal. A waveform
14
represents a voltage of a bit line while reading data from a row nearest the sense amplifiers. A waveform
16
represents a voltage of the bit line while reading data from a row furthest from the sense amplifiers.
The read access begins with a precharge cycle that includes pulsing the precharge signal
10
for a fixed duration. The precharge cycle causes all bit lines to be charged to a predetermined initial voltage
18
. The distributed RC effect of the bit lines results in portions of the bit lines close to the precharge circuitry to reach the predetermined initial voltage
18
before portions of the bit lines far from the precharge circuitry. An example of a precharging delay along the bit lines between the furthest and nearest portions is shown as a delay
20
.
After the precharge cycle has completed, a sensing cycle is performed. The sensing cycle involves asserting the wordline signal
12
for a selected row within the conventional memory until a known value stored in a dummy bit cell within the selected row triggers a dummy sense amplifier, as represented by a line
22
. A voltage differential induced in the bit lines by a bit cell in the nearest row will be detected at a time
24
. A voltage differential induced in the bit lines by a bit cell in the furthest row will be detected at a later time
26
. The difference in the time
24
to the time
26
is a delay
28
that represents a spread in the memory access times.
SUMMARY OF THE INVENTION
The present invention concerns a memory circuit generally comprising a sense amplifier, an array of bit cells, a plurality of bit lines, and a circuit. The array of bit cells may include a far bit cell disposed in the array opposite the sense amplifier. The bit lines may couple the bit cells to the sense amplifier. The circuit may be configured to assert a far wordline signal controlling the far bit cell during a precharge cycle for the bit lines.
The objects, features and advantages of the present invention include providing a method and/or architecture for equalized memory access times that may (i) provide closer access time variations among the bit cells regardless of where in the memory the data is being accessed and/or (ii) be easily integrated into a design without any detrimental impact.
REFERENCES:
patent: 6108256 (2000-08-01), Schneider
patent: 6125071 (2000-09-01), Kono
patent: 6191988 (2001-02-01), DeBrosse
patent: 6198682 (2001-03-01), Proebsting
patent: 6335904 (2002-01-01), Tsuchida
patent: 6373753 (2002-04-01), Proebsting
patent: 6392911 (2002-05-01), Han
patent: 2002/0027830 (2002-03-01), Tsuchida et al.
patent: 2002/0036929 (2002-03-01), Koizumi et al.
LSI Logic Corporation
Maiorana P.C. Christopher P.
Nguyen Hien
Nguyen Viet Q.
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