Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-04-12
2005-04-12
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S158000, C438S300000, C438S153000, C438S283000, C438S220000, C438S471000, C438S289000, C257S372000, C257S376000, C257S049000, C257S050000, C257S041000, C257S042000, C257S048000
Reexamination Certificate
active
06878595
ABSTRACT:
The present invention relates to a technique that can be used to reduce the sensitivity of integrated circuits to a failure mechanism to which some integrated circuits (ICs) are susceptible, known as latchup. The present invention relates to a scheme for suppressing latchup sensitivity by a step to be performed after the IC has been manufactured, rather than being a step in the normal production process. The process involves exposing silicon, either in wafer or die form, to energetic ions, such as protons (hydrogen nuclei) or heavier nuclei (e.g. argon, copper, gold, etc.), having energy sufficient to penetrate the silicon from the back of the wafer or die to within a well-defined distance from the surface of the silicon on which the integrated circuit has been formed (the front surface). The ions will enter the silicon through the surface of the silicon opposite to the surface onto which the integrated circuit has been formed (the back surface), will travel through the silicon, and will be completely stopped within a narrow, controlled distance from the front surface. This very high energy ion implantation will change the properties of silicon in such a way that the process or processes responsible for latchup are inhibited, either from the structural damage done to the single crystal, or from changes in the electrical properties of the silicon due to the chemical properties of the implanted ions, or both. Since the implanted ions all stop within a narrow region, spaced away from the region in which the components of the integrated circuit are located, the functionality and parameters of the IC are not degraded. Consequently, the procedure of the present invention is a method of processing silicon wafers or die so that the sensitivity of the ICs on this wafer or die to latchup is reduced or eliminated.
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Full Circle Research, Inc.
Meads Robert R.
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