Technique for reducing 1/f noise in MOSFETs

Details Technique for reducing 1/f noise in MOSFETs Technique for reducing 1/f noise in MOSFETs

2000-06-28

2003-02-04

Lebentritt, Michael (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S766000, C438S770000, C438S786000

Reexamination Certificate

active

06514825

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to microelectronic circuits. More specifically, the present invention relates to reducing 1/f noise in Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices.
2. Background Information
Nitrided oxides are commonly used as gate dielectrics in submicron Complementary Metal-Oxide Semiconductor (CMOS) technologies due to the nitrogen's ability to control boron penetration from the p+ doped polycrystalline silicon into the channel region of the MOSFET device. The control of boron penetration is critical in establishing and maintaining a uniform and stable value of threshold voltage (Vth) for the MOSFET device. Changes in the boron penetration produce fluctuations in the threshold voltage which impact the performance of the device. It is critical that the MOSFET device has a predictable threshold voltage so that the device can be accurately matched to the required specifications. In a dual gate thickness CMOS process technology, where thin and thick gate oxides for MOSFET devices are formed, boron penetration is generally only a problem for thin gate oxide MOSFETs.
Unfortunately, nitrided oxides introduce some undesirable side effects. The use of nitrided oxides significantly increases the 1/f noise or “flicker noise” in MOSFETs through an introduction of oxide charges and traps. For example, referring now to
FIG. 1A
, the noise measurement of a n-channel thick gate oxide MOSFET fabricated with and without nitrided oxide, is plotted over a range of 1-10000 Hz. Noise measurement
100
corresponds to a n-channel MOSFET fabricated with pure oxide (i.e., without nitrogen) and noise measurement
110
corresponds to a n-channel MOSFET fabricated with nitrided oxide. As can be seen by the graph in
FIG. 1A
, nitridation increases 1/f noise by approximately 5.3 dB over the corresponding NFET device grown in silicon dioxide (SiO
2
) without nitrogen. Similarly, referring now to
FIG. 1B
, noise measurement
150
corresponds to a p-channel thick gate oxide MOSFET fabricated with pure oxide and noise measurement
160
is for the corresponding p-channel MOSFET fabricated with nitrided oxide. In this case, nitridation causes a 1/f noise increase of 13.7 dB for a buried channel PFET. These levels of 1/f noise are particularly unattractive for analog/RF circuit applications due to the impact upon key circuit metrics such as noise figure and oscillator phase noise.
Vertical High Pressure (VHP) nitridation followed by reoxidation to push nitrogen away from the silicon-oxide interface has been tried as a method for reducing 1/f noise, while maintaining the benefit of controlling boron penetration. However, VHP nitridation requires the use of a very high pressurized reacting chamber that is very expensive to utilize in a manufacturing process. Further, VHP nitridation is hard to implement because of safety reasons.
Therefore, a technique for controlling boron penetration is thus needed which overcomes the shortcomings of the prior art.
SUMMARY OF THE INVENTION
A method of forming a gate for a MOSFET device in accordance with the present invention utilizes a process of implanting nitrogen into the device substrate proximate the gate. The nitrogen implant process provides the benefit of controlling boron penetration into the channel regions of thin gate MOSFET devices while reducing the amount of 1/f noise in thick gate MOSFET devices. Thus, a practical embodiment may be realized in a cost efficient manner.
The above and other features of the present invention may be carried out in one form by forming a sacrificial oxide layer on a semiconductor substrate using thermal oxidation. A photoresist pattern is then defined so as to expose regions where thin gate oxide will eventually be formed. Next, nitrogen is selectively implanted into the thin gate regions so that it penetrates the semiconductor substrate. The photoresist and sacrificial oxide layer are then etched to expose the underlying semiconductor substrate layer. A gate oxide layer is then formed from an upper portion of the substrate layer. Next, a polysilicon layer is formed on the gate oxide layer, and then the polysilicon layer is patterned and etched to form a gate electrode.


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Article entitled 1/f Noise Characterization of Deep Sub-Micron Dual Thickness Nitrided Gate Oxide n- and p-MOSFETs, by Sandeep D'Souza et al., pp. 1-4, Dec. 1999.
Article entitled “Simultaneious Growth of Different Thickness Gate Oxides in Silicon CMOS Processing”, by Brian Doyle et al., IEEE Electron Device Letters, vol. 16, No. 7, pp. 301-302, Jul. 1995.

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