Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
1997-11-14
2001-01-16
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S404000, C438S410000, C438S425000
Reexamination Certificate
active
06174784
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to methods and apparatus for isolating semiconductor devices with silicon on insulator technology, and in particular, for forming isolated silicon islands using sub-micron technology.
BACKGROUND OF THE INVENTION
The advantages of silicon on insulator (SOI) technology for complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) are well documented. In general, undesired p-n junction capacitance between a source/drain and a substrate is reduced by approximately twenty-five-percent when using SOI technology. Furthermore, active current consumption is less and device access time is equivalent to that of similar devices formed on bulk-silicon substrates. Other advantages of SOI technology include suppression of the short channel effect, suppression of the body-effect, high punch-through immunity, and freedom from latch-up and soft errors. As the demand increases for battery-operated equipment, SOI technology is becoming increasingly more popular due to its low power requirements and high speeds.
There are many different techniques for isolating devices in ICs. A technique is selected according to its different attributes, such as: minimum isolation spacing, surface planarity, process complexity, and density of defects generated during fabrication.
SIMOX (Separation by IMplanted OXygen) technology is one method for forming SOI structures. SIMOX entails implanting a high dose of oxygen ions at a sufficiently deep level within a silicon substrate. A subsequent anneal step forms a buried oxide layer in the substrate. After the anneal step, an additional layer of epitaxial silicon is usually deposited to obtain a sufficiently thick silicon layer on which to form a device. Disadvantages of using SIMOX include its high expense and yield loss, which undesirably decreases achievable chip density.
Another technique for forming an isolation layer in a substrate is by the wafer bonding method. Using this technique, two oxidized silicon wafers are fused together through a high-temperature furnace step. However, this technique increases the substrate thickness, which is often a critical dimension. Furthermore, wafer bonding techniques are often plagued by low production yield due to particles/voids, which prevent adequate bonding between the two wafers in such areas.
Another technique used for forming an isolation layer in a substrate is by forming silicon islands through a series of etch and oxidation steps. For example, U.S. Pat. No. 4,604,162 (hereinafter the '162 patent) uses a series of a pad oxide layer, a silicon nitride layer, and a silicon dioxide layer, which is photolithographically masked and anisotropically etched to define silicon islands capped with a silicon nitride layer. Then, a second anisotropic etch (such as a reactive ion etch (RIE)) removes further substrate material between the silicon islands. The depth of the second anisotropic etch is proportional to the width of the silicon islands. A subsequent oxidation step forms silicon dioxide, undercutting the silicon islands and isolating each of them from surrounding regions. However, this technique has not been used commercially because it is too costly and consumes too much time to oxidize an area having an effective width as great as that of the feature size. Another disadvantage of this technique is that the resulting isolated silicon structure has excess mechanical stress and crystal damage at each of its corners, due to oxidation around the entirety of each individual island, which is necessary for its complete isolation. Furthermore, the method described in the patent application requires an additional planarization step, which adds complexity to the fabrication process.
There is a need for an effective isolation technique for sub-micron semi-conductor technology that is efficient and simple. A primary concern in the fabrication of ICs is simplicity and minimization of process steps. There is a need for an isolation technique that is inexpensive and compatible with large volume CMOS manufacturing technology. Furthermore, an isolation technique, which allows fabrication of highly dense ICs without increasing the dimensions of the IC is needed.
SUMMARY OF THE INVENTION
Silicon on insulator (SOI) rows and islands are formed for subsequent sub-micron device formation. For example, complementary metal-oxide-semiconductor (CMOS) transistors are later formed on such SOI rows, isolated from each other using standard techniques, such as LOCal Oxidation of Silicon (LOCOS). To form the rows, trenches are directionally-etched in a silicon substrate, leaving rows of silicon between the trenches.
Silicon nitride is then deposited over the trenches, extending partly down the sides of the trenches. An isotropic chemical etch is then used to partially undercut narrow rows of silicon in the substrate. It is important to use an isotropic etch for this step to compensate for the volume of oxide to be formed. In general, the volume of oxide formed is approximately twice that of the silicon consumed. Furthermore, an isotropic etch is necessary to advantageously minimize the subsequent oxidation time needed to fully undercut the silicon rows. The subsequent oxidation step fully undercuts the rows of silicon, isolating the silicon rows from adjacent active areas.
One advantage of this invention is that by using narrow, sub-micron rows of silicon and appropriately designed process conditions, generally planar structures are formed in an integrated circuit (IC). The larger volume of oxide fills the trenches between the rows. This avoids complex and expensive planarization techniques, such as employed in older micron dimension technologies. Furthermore, such oxidation minimizes mechanical stress and crystal damage in resulting structures, when used to finish undercutting rows, as compared to undercutting individual silicon islands.
This invention enables formation of sub-micron devices, such as CMOS transistors, having a high chip density, without increasing the dimensions of the IC. This method yields isolated active regions, having a high degree of regularity and yield, formed in an inexpensive manner. This method is compatible with CMOS IC manufacturing technology due to its simplicity and minimal number of process steps. Regular array structures, such as dynamic random access memories (DRAMs) particularly benefit from this invention, separated on the silicon rows using LOCOS technology.
REFERENCES:
patent: 3407479 (1968-10-01), Fordemwalt et al.
patent: 3457123 (1969-07-01), Van Pul
patent: 3471754 (1969-10-01), Hoshi et al.
patent: 3689357 (1972-09-01), Jordan
patent: 4419150 (1983-12-01), Soclof
patent: 4437226 (1984-03-01), Soclof
patent: 4561932 (1985-12-01), Gris et al.
patent: 4580331 (1986-04-01), Soclof
patent: 4604162 (1986-08-01), Sobczak
patent: 4625391 (1986-12-01), Sasaki
patent: 4685198 (1987-08-01), Kawakita et al.
patent: 4755481 (1988-07-01), Faraone
patent: 4763183 (1988-08-01), Ng et al.
patent: 4845048 (1989-07-01), Tamaki et al.
patent: 5001526 (1991-03-01), Gotou
patent: 5177028 (1993-01-01), Manning
patent: 5234535 (1993-08-01), Beyer et al.
patent: 5391911 (1995-02-01), Beyer et al.
patent: 5426070 (1995-06-01), Shaw et al.
patent: 5441591 (1995-08-01), Imthurn et al.
patent: 5466625 (1995-11-01), Hsieh et al.
patent: 5483487 (1996-01-01), Sung-Mu
patent: 5492853 (1996-02-01), Jeng et al.
patent: 5497017 (1996-03-01), Gonzales
patent: 5528062 (1996-06-01), Hsieh et al.
patent: 5640342 (1997-06-01), Gonzalez
patent: 5691230 (1997-11-01), Forbes
patent: 5710057 (1998-01-01), Kenney
patent: 5773152 (1998-06-01), Okonogi
Abe, et al., “Silicon Wafer-Bonding Process Technology for SOI Structures”, Conference on Solid State Devices and Materials, Sponsored by The Japan Society of Applied Physics, 853-856, (1990).
Auberton-Herve, A.J., “SOI: Materials to Systems”, Digest of the International Electron Device Meeting, San Francisco, 3-10, (Dec. 1996).
Cartagena, et al., “Bonded Etchback Silicon on Sapphire Bipolar Junction Transistors”, In: The Electroc
Dang Trung
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
LandOfFree
Technique for producing small islands of silicon on insulator does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Technique for producing small islands of silicon on insulator, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Technique for producing small islands of silicon on insulator will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2541275