Technique for implementing chipkill in a memory system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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Reexamination Certificate

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07096407

ABSTRACT:
A technique for handling errors in a memory system. Specifically, a new dual mode ECC algorithm is provided to detect errors in memory devices. Further, an XOR memory engine is provided to correct the errors detected in the dual mode ECC algorithm. Depending on the mode of operation of the dual mode ECC algorithm and the error type (single-bit or multi-bit), errors may be corrected using ECC techniques. If X16 or X32 memory devices are implemented, a technique for striping the data from each memory device is implemented to detect errors in the X16 and X32 devices.

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Timothy J. Dell, A white Paper on the Benefits of Chipkill-Correct ECC for PC Server main Memory.□□IBM Microelectronics Division—Rev Nov. 19, 1997.
David Locklear, Chipkill Correct Memory Architecture.□□Dell Enterprise Sysyems Group. Aug. 2000.

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