Technique for generating memory clock in video controller

Details Technique for generating memory clock in video controller Technique for generating memory clock in video controller

1998-09-14

2000-08-29

Palys, Joseph E.

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Multiple or variable intervals or frequencies

713400, G06F 104, G06F 112

Patent

active

061123102

ABSTRACT:
A video controller for automatically varying a memory clock frequency according to the number of commands of controlling a memory includes: a video memory for storing image data to be transmitted to a monitor, a bus interface for receiving commands transmitted from a central processing unit (CPU) through a host bus, a controller for generating an address, data and a control signal for controlling reading from and writing into the video memory according to the commands received from the bus interface, a frequency setter for variably setting a memory clock frequency for accessing a video memory according to an occupancy rate of video access cycles with respect to total bus cycles, and a frequency generator for generating a memory clock according to the memory clock frequency set by the frequency setter. When the number of memory access cycles increases, the memory clock frequency increases to improve the performance of the system and when the number of memory access cycles is reduced, the memory clock frequency is also reduced, to minimize power consumption of the chip.

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