Technique for forming an oxide/nitride layer stack by...

Details Technique for forming an oxide/nitride layer stack by... Technique for forming an oxide/nitride layer stack by...

2003-05-22

2004-04-20

Ghyka, Alexander (Department: 2812)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

By reaction with substrate

C438S763000, C438S769000

Reexamination Certificate

active

06723663

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
Generally, the present invention relates to the field of fabricating microstructures, such as integrated circuits, micromechanical structures and the like, and, more particularly, to the formation of an ultra-thin dielectric oxide layer having increased resistance against migration of charge carriers through the dielectric oxide layer.
2. Description of the Related Art
Presently, microstructures are integrated into a wide variety of products. One example in this respect is the employment of integrated circuits that, due to their relatively low cost and high performance, are increasingly used in many types of devices, thereby allowing superior control and operation of those devices. Due to economic reasons, manufacturers of microstructures, such as integrated circuits, are confronted with the task of steadily improving performance of these microstructures with every new generation appearing on the market. However, these economic constraints not only require improving the device performance but also demand a reduction in size so as to provide more functionality of the integrated circuit per unit chip area. Thus, in the semiconductor industry, ongoing efforts are being made to reduce the feature sizes of feature elements. In present-day technologies, the critical dimension of these elements approach 0.1 &mgr;m and less. In producing circuit elements of this order of magnitude, along with many other issues especially arising from the reduction of feature sizes, process engineers face several issues. For example, one such issue involves providing extremely thin dielectric layers on an underlying material layer, wherein certain characteristics of the dielectric layer, such as permittivity and/or resistance against charge carrier tunneling and the like, have to be improved without sacrificing the physical properties of the underlying material layer.
One important example in this respect is the formation of ultra-thin gate insulation layers of field effect transistors, such as MOS transistors. The gate dielectric of a transistor has an essential impact on the performance of the transistor. As is commonly known, reducing the size of a field effect transistor, that is reducing the length of a conductive channel that forms in a portion of a semiconductor region by applying a control voltage to a gate electrode formed on the gate insulation layer, also requires the reduction of the thickness of the gate insulation layer to maintain the required capacitive coupling from the gate electrode to the channel region. Currently, most of the highly sophisticated integrated circuits, such as CPUs, memory chips and the like, are based on silicon and, therefore, silicon dioxide has preferably been used as the material for the gate insulation layer due to the well-known and superior characteristics of the silicon dioxide/silicon interface. For a channel length on the order of 100 nm and less, however, the thickness of the gate insulation layer has to be reduced to about 2 nm in order to maintain the required controllability of the transistor operation. Steadily decreasing the thickness of the silicon dioxide gate insulation layer, however, leads to an increased leakage current therethrough, thereby resulting in an unacceptable increase of static power consumption as the leakage current exponentially increases for a linear reduction of the layer thickness.
Therefore, great efforts are presently being made to replace silicon dioxide by a dielectric exhibiting a higher permittivity so that a thickness thereof may be higher than the thickness of a corresponding silicon dioxide layer providing the same capacitive coupling. A thickness for obtaining a specified capacitive coupling will also be referred to as capacitive equivalent thickness and determines the thickness that would be required for a silicon dioxide layer. It turns out, however, that it is difficult to incorporate high-k materials into the conventional integration process and, more importantly, the provision of a high-k material as a gate insulation layer seems to have a significant influence on the carrier mobility in the underlying channel region, thereby remarkably reducing the carrier mobility and thus the drive current capability. Hence, although an improvement of the static transistor characteristics may be obtained by providing a thick high-k material, at the same time, an unacceptable degradation of the dynamic behavior presently makes this approach less than desirable.
A different approach that is currently favored is the employment of an integrated silicon oxide
itride layer stack that may reduce the gate leakage current by 0.5 to 2 orders of magnitude while maintaining compatibility with standard CMOS process techniques. It has been found that the reduction of the gate leakage current mainly depends upon the nitrogen concentration incorporated into the silicon dioxide layer by means of plasma nitridation. Although this approach seems to relax the issue of gate dielectric leakage for the present circuit generation, this approach does not seem to allow further aggressive dielectric thickness scaling required for future device generations. To more clearly demonstrate the problems involved in the conventional process technique, a typical process flow for forming a gate insulation layer, including a nitride/silicon dioxide layer, will now be described with reference to
FIGS. 1
a
-
1
e.
In
FIG. 1
a
, a semiconductor device
100
comprises a silicon substrate
101
, in which an active region
103
is defined by shallow trench isolations
102
. A thin dielectric base layer
110
, for example formed of a grown oxide layer, covers the active region
103
. Moreover, the semiconductor device
100
is exposed to a nitrogen-containing plasma, indicated by reference sign
104
.
Typically, the semiconductor device
100
may be formed according to the following process sequence. After formation of the shallow trench isolation
102
and various implantation steps to generate a required well dopant profile (not shown) in the active region
103
, the dielectric base layer
110
is formed by a conventional oxidation process or by a rapid thermal oxidation process. Subsequently, the semiconductor device
100
is exposed to the nitrogen-containing plasma
104
to introduce nitrogen ions into the silicon dioxide layer
110
to improve, as explained above, the resistance of the dielectric base layer
110
against charge carrier migration and to increase the permittivity thereof. An energy of the ions in the nitrogen-containing plasma
104
is substantially determined by the difference between the plasma potential and the floating potential of the semiconductor device
100
, wherein this voltage is difficult to adjust or even may not be adjustable at all. The ion density and, thus, the nitridation rate depends on process parameters, such as the high frequency (HF) power, the temperature of the plasma ambient
104
, the pressure thereof, and the like.
As is well known, nitrogen atoms, introduced into the active region
103
and thus into the channel region of the transistor device to be formed, significantly affect the electrical characteristics of the transistor device in that both the crystallinity of the active region
103
is deteriorated and the charge carrier mobility is degraded. Consequently, the introduction of nitrogen into the active region
103
has to be suppressed as much as possible in view of a required high transistor performance. On the other hand, a thickness of the dielectric base layer
110
is to be scaled down in conformity with the device dimensions which would, however, at a certain minimum dielectric thickness, lead to an increased penetration of nitrogen ions into the active region
103
during the plasma treating
104
. As a consequence, there exists a severe trade-off between the improvement of the transistor device performance by scaling down the dielectric base layer
110
and the device degradation caused by the incorporation of nitrogen into the active region
103
.
FI

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