Technique for forming a transistor having raised drain and...

Details Technique for forming a transistor having raised drain and... Technique for forming a transistor having raised drain and...

2007-10-09

2007-10-09

Coleman, W. David (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21619

Reexamination Certificate

active

11280484

ABSTRACT:
By providing a hard mask layer stack including at least three different layers for patterning a gate electrode structure, constraints demanded by sophisticated lithography, as well as cap layer integrity, in a subsequent selective epitaxial growth process may be accomplished, thereby providing the potential for further device scaling of transistor devices requiring raised drain and source regions.

REFERENCES:
patent: 6573030 (2003-06-01), Fairbairn et al.
patent: 6800530 (2004-10-01), Lee et al.
patent: 7037794 (2006-05-01), Beintner et al.
patent: 7084071 (2006-08-01), Dakshina-Murthy et al.
patent: 2004/0137672 (2004-07-01), Lee et al.
patent: 0 517 627 (1992-06-01), None

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