Technique for forming a transistor having raised drain and...

Details Technique for forming a transistor having raised drain and... Technique for forming a transistor having raised drain and...

2006-12-05

2006-12-05

Pham, Thanhha S. (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S301000, C438S305000

Reexamination Certificate

active

07144786

ABSTRACT:
By using sidewall spacers adjacent to a gate electrode structure both as an epitaxial growth mask and an implantation mask, the complexity of a conventional process flow for forming raised drain and source regions may be significantly reduced, thereby reducing production costs and enhancing yield by lowering the defect rate.

REFERENCES:
patent: 5200352 (1993-04-01), Pfiester
patent: 6137149 (2000-10-01), Kodama
patent: 6254676 (2001-07-01), Yang et al.
patent: 6255182 (2001-07-01), Wieczorek et al.
patent: 6316303 (2001-11-01), Lin et al.
patent: 6489206 (2002-12-01), Chen et al.
patent: 6506649 (2003-01-01), Fung et al.
patent: 6555437 (2003-04-01), Yu

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