Technique for etching a low capacitance dielectric layer

Details Technique for etching a low capacitance dielectric layer Technique for etching a low capacitance dielectric layer

1999-06-30

2004-02-24

Hiteshew, Felisa C. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S700000, C438S710000, C438S713000

Reexamination Certificate

active

06696366

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to the fabrication of semiconductor integrated circuits (IC's). More particularly, the present invention relates to improved techniques for etching through an IC layer stack, including a low capacitance dielectric layer, during IC fabrication.
In the manufacturing of certain semiconductor integrated circuits, a low dielectric constant (low-K) material may sometimes be employed as the material in a dielectric layer in order to reduce the capacitance of devices that are formed and to improve their electrical performance. As in all dielectric layers, there is typically a need to etch vias or trenches through the dielectric layer in order to form metal interconnects therethrough. The process of forming a via/trench through the low capacitance dielectric layer is described below.
To facilitate discussion,
FIG. 1
illustrates a representative layer stack
100
, including a photoresist layer
102
, a hard mask layer
104
, a low capacitance dielectric layer
106
, and an etch stop layer
108
. Etch stop layer
108
may represent, for example, an etch stop layer for a dual damascene process and is typically formed of a suitable etch stop material such as TiN, SiN, TEOS, or the like. Low capacitance dielectric layer
106
represents a layer of organic low-K material such as SILK by Dow Chemical, Flare by Allied Signal, BCB by Dow Chemical, Parylene by Novellus, or the like. The etch chemistry may also etch non-low-K materials such as organic films like photoresist.
Above low capacitance dielectric layer
106
, there is shown disposed a hard mask layer
104
, which is typically formed of a material such as SiN, SiON (silicon oxynitride) or TEOS. Hard mask layer
104
represents the masking layer that is employed to etch the via/trench in low capacitance dielectric layer
106
. The hard mask layer is employed since photoresist is typically ineffective as a masking material when etching the organic low-K material of low capacitance dielectric layer
106
. This is because the photoresist material and the organic low-K material tend to have similar chemical characteristics, tend to require a similar etch chemistry, and/or tend to have a similar etch rate. To pattern the hard mask out of hard mask layer
104
, photoresist layer
102
is provided. Photoresist layer
102
may represent, for example, a layer of deep UV or conventional photoresist material.
In
FIG. 2
, photoresist layer
102
is patterned using a conventional photoresist patterning process. The patterning of photoresist layer
102
creates an opening
202
through which hard mask layer
104
may be etched in a subsequent hard mask etch process.
In
FIG. 3
, a hard mask etch process is employed to extend opening
202
through hard mask layer
104
. In one example, hard mask layer
104
represents a TEOS layer, and the hard mask etch process may take place in a plasma processing reactor using a suitable TEOS etch chemistry such as Ar/C
4
F
8
/C
2
F
6
/O
2
or a conventional TEOS etchant.
In
FIG. 4
, the low capacitance dielectric layer
106
is being etched. The etching of low capacitance dielectric layer
106
typically takes place in a plasma processing reactor. Low capacitance dielectric layer
106
is typically etched using an oxygen-containing gas (such as O
2
, CO, CO
2
, or the like). A diluent such as N
2
is typically added to the etchant gas employed to etch through the low capacitance dielectric material. For reasons which shall be explained shortly hereinafter, a passivating agent such as a fluorocarbon gas is also typically added to the etch chemistry.
As is well known, the oxygen species employed to etch through low capacitance dielectric layer
106
tends to etch isotropically, causing the sidewalls in opening
202
to bow instead of maintaining the desired vertical sidewall profile.
FIG. 5
illustrates the bowing sidewall that occurs when the etch is allowed to proceed isotropically through low capacitance dielectric layer
106
. The bowing effect is exacerbated if over-etching is required to compensate for etch nonuniformity across the wafer. This bowing effect degrades profile control, for example, causing the formation of re-entrant profiles , which are profiles that have angles greater than 90 degrees, and cause difficulties in subsequent processing steps such as metal fill.
To maintain profile control and prevent the aforementioned sidewall bowing problem, in addition to the oxygen-containing gas, the prior art typically employs a fluorocarbon such as C
4
F
8
, C
2
HF
5
, CH
2
F
2
, or the like as a passivating agent. However, while the addition of the fluorocarbon passivating agent helps preserve the vertical sidewall profile, it tends to facet first the photoresist and subsequently the hard mask, which in turn enlarges opening
202
as the etch proceeds through low capacitance dielectric layer
106
.
To elaborate, the oxygen species that is employed to etch through the low capacitance dielectric layer
106
also attacks the overlying photoresist material in photoresist layer
102
. Consequently, the thickness of photoresist layer
102
is reduced as the etch proceeds through low capacitance dielectric layer
106
. Because the oxygen species attacks the photoresist material isotropically, the photlresist mask often pulls back in regions
402
and
404
of the via/trench. As the photoresist material is worn away by the oxygen species and the photoresist material is pulled back in regions
402
and
404
as shown in
FIG. 4
, the TEOS hard mask material of hard mask layer
104
is exposed to the fluorocarbon etchant that is added for passivation purposes. Since fluorocarbon is an etchant of TEOS, the exposed hard mask material in regions
408
and
410
are also etched away as time goes on, causing the opening in hard mask layer
104
to enlarge. The enlargement of the opening in hard mask layer
104
in turn enlarges the via/trench to be etched through low capacitance dielectric layer
106
. With this enlargement, the critical dimension of the via/trench are lost or destroyed. The result is shown in
FIG. 6
wherein the resultant via/trench has a larger cross-section than intended, where width (w) indicates the intended cross-section.
The use of a fluorocarbon additive also narrows the process window of the low capacitance dielectric layer etch. If too much fluorocarbon is added to the etch chemistry, the etch rate of the low capacitance dielectric layer will be reduced dramatically, until etch stoppage eventually occurs. If too little fluorocarbon is added, there may be insufficient passivation to maintain the desired vertical sidewall profile.
In view of the foregoing, there is a need for improved techniques for etching through a low capacitance dielectric layer while maintaining profile control, preserving critical dimension of the resultant via/trench, and maintaining a high etch rate.
SUMMARY OF THE INVENTION
The present invention relates to a method for etching through a low capacitance dielectric layer in a plasma processing chamber. The method uses an etch chemistry that includes N
2
, O
2
, and a hydrocarbon into the plasma processing chamber. The present invention yields not only fast etch rates but also maintains profile control and preserves critical dimension of the resultant opening (e.g., via/trench) being etched in the low capacitance layer.
In one embodiment, the present invention relates to a method for etching through a low capacitance dielectric layer in a plasma processing chamber. The low capacitance dielectric layer is disposed below a hard mask layer on a substrate. The method includes flowing an etch chemistry that includes N
2
, O
2
, and a hydrocarbon into the plasma processing chamber. A plasma is then created out of the etch chemistry. The method also includes etching, using the plasma, through the low capacitance dielectric layer through openings in the hard mask layer.
In accordance with another embodiment, the etch chemistry further includes a fluorocarbon-containing gas. The fluorocarbon-containing gas chemis

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