Technique for debugging an integrated circuit having a...

Details Technique for debugging an integrated circuit having a... Technique for debugging an integrated circuit having a...

2005-09-06

2005-09-06

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S736000

Reexamination Certificate

active

06941498

ABSTRACT:
The present disclosure describes a technique for debugging an integrated circuit having a parallel scan-chain architecture. Blocking circuits are introduced at the inputs and/or outputs of scan-chain branches. The blocking circuits allow the inputs to and/or the outputs from the scan-chain branches to be selectively blocked. This allows individual scan-chain branches to be isolated and debugged.

REFERENCES:
patent: 5668490 (1997-09-01), Mitra et al.
patent: 5983380 (1999-11-01), Motika et al.
patent: 6145105 (2000-11-01), Nadeau-Dostie et al.
patent: 6557129 (2003-04-01), Rajski et al.
Ilker Hamzaoglu et al., Reducing Test Application Time For Build-in-Self-Test Test Pattern Generators, IEEE VLSI Test Symposium (Apr. 2000), (7 pgs.).

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