Technique for controlling system bus timing with on-chip...

Details Technique for controlling system bus timing with on-chip... Technique for controlling system bus timing with on-chip...

1998-11-06

2001-09-11

Heckler, Thomas M. (Department: 2182)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

Reexamination Certificate

active

06289468

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH
Not applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to controlling system bus timing of an embedded system with programmable delay lines, and more specifically to controlling dynamic random access memory (DRAM) associated timing as well as the timing of devices that include an input that is not synchronous to a system clock with programmable delay lines.
2. Description of the Related Art
Embedded systems are generally specialized computer systems that are part of a larger system or machine. Embedded systems have been implemented in various consumer electronics which include watches, microwave ovens, video cassette recorders, and automobiles. A typical embedded system is preprogrammed to perform a dedicated or narrow range of functions with minimal user intervention. In those embedded systems an operating system and various programs are stored in read only memory (ROM). A typical embedded system includes a processor, memory (such as dynamic random access memory (DRAM)), and related peripherals on a single circuit board.
DRAM addressing has normally been accomplished in two stages. In a typical application an address buffer, within the DRAM, initially reads a row address and then reads a column address. These addresses are multiplexed with the multiplexing being controlled by row address strobe (RAS) and column address strobe (CAS) signals. The RAS signal, when asserted, directs the DRAM to accept the address provided as the row address and interpret it accordingly. The CAS signal, when asserted, directs the DRAM to accept the address provided as the column address and interpret it accordingly. In order for the DRAM to function as designed, the duration of the RAS and CAS signals, as well as the time interval between the signals, must meet the specification of the DRAM that is utilized in the embedded system. External delay lines have been utilized to adjust DRAM related timing.
In a typical embedded system each bank of DRAM has similar timing requirements. In those systems, an engineer who tailors memory timing for maximum efficiency of a DRAM bank maximizes efficiency of a memory subsystem.
SUMMARY OF THE INVENTION
An embodiment of the present invention provides an embedded system that is capable of controlling DRAM associated timing. More generally, according to the invention programmable delay lines are provided in a microcontroller to timing critical pads. These programmable delay lines are analog and are not dependent on a system clock. In the disclosed embodiment a delay register is coupled to a processor. The delay register stores a delay or control value responsive to the processor. A delay line or plurality of delay lines are coupled to the delay register and delay a signal responsive to the delay value. In a disclosed embodiment, the signal is a row address strobe (RAS) memory signal. In another embodiment, the signal is a column address strobe (CAS) memory signal.
The delay lines can be programmed, such as by adding delay components in response to the delay register. An advantage of an embodiment of the present invention is that it allows a designer to utilize DRAM with different timing requirements in the embedded system. The programmable delay lines allow for relaxed timing for slower DRAM and tighter timing for faster DRAM. In addition, the invention is applicable to other peripherals or components that have different timing requirements.


REFERENCES:
patent: 4675546 (1987-06-01), Shaw
patent: 5448699 (1995-09-01), Goss et al.
patent: 6058496 (2000-05-01), Gillis et al.

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