Task concurrency management design method

Details Task concurrency management design method Task concurrency management design method

2007-06-11

2010-11-09

Garbowski, Leigh Marie (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07831951

ABSTRACT:
A system and method of designing digital system. One aspect of the invention includes a method for designing an essentially digital system, wherein Pareto-based task concurrency optimization is performed. The method uses a system-level description of the functionality and timing of the digital system. The system-level description comprises a plurality of tasks. Task concurrency optimization is performed on said system-level description, thereby obtaining a task concurrency optimized system-level description, including Pareto-like task optimization information. The essentially digital system is designed based on said task concurrency optimized system-level description. In one embodiment of the invention, the description is includes a “grey-box” description of the essentially digital system.

REFERENCES:
patent: 5202975 (1993-04-01), Rasbold et al.
patent: 5327561 (1994-07-01), Choi et al.
patent: 5594864 (1997-01-01), Trauben
patent: 5664193 (1997-09-01), Tirumalai
patent: 5742814 (1998-04-01), Balasa et al.
patent: 5930510 (1999-07-01), Beylin et al.
patent: 5978509 (1999-11-01), Nachtergaele et al.
patent: 6064819 (2000-05-01), Franssen et al.
patent: 6078745 (2000-06-01), De Greef et al.
patent: 6151705 (2000-11-01), Santhanam
Al-Furiah et al., “Memory Hierarchy Management for Interactive Graph Structures”, Proceedings, IEEE International Symposium on Parallel and Distributed Processing, Mar.-Apr. 1998.
Al-Mouhamed, M., et al., “A Heuristic Storage for Minimizing Access Time of Arbitrary Data Patterns”, IEEE Transactions on Parallel and Distributed Systems, vol. 8, No. 4, Apr. 1997, pp. 441-447.
Balasa, F., et al., “Dataflow-Driven Memory Allocation for Multi-Dimensional Signal Processing Systems”, Proceedings IEEE International Conference on Computer Aided Design, San Jose, CA, pp. 31-34, Nov. 1994.
Catthoor et al., “Global Communication and Memory Optimizing Transformations for Low Power Signal Processing Systems”, IEEE workshop on VLSI signal processing, 1994, pp. 178-187.
Catthoor et al., “System-Level Data-Flow Transformations for Power Reduction in Image and Video Processing”, Proceedings of the Third IEEE International Conference on Electronics, Circuits and Systems, 1996, pp. 1025-1028.
Catthoor, “Power-Efficient Data Storage and Transfer Methodologies: Current Solutions and Remaining Problems”, IEEE Computer Society Workshop on VLSI System Level Design, 1998, 7 pages.
Catthoor et al., “Proposal for Unified System Design Meta Flow in Task-Level and Instruction-Level Design Technology Research for Multi-Media Applications”, Proceedings on the 11thInternational Symposium on System Synthesis, pp. 89-95, Dec. 1998.
Chen, Tien-Fu et al., A Hierarchical Memory Directory Scheme via Extending SCI for Large Scale Multiprocessors, High Performance Computing on International Superhighway, Apr.-May 1997, pp. 18-23.
Danckaert et al., “System Level Memory Optimization for Hardware-Software Co-Design”, Proceedings of the Fifth International Workshop on Hardware/Software Co-Design, 1997, pp. 55-59.
De Greef, E., et al., “Mapping Real-Time Motion Estimation Type Algorithms to Memory Efficient, Programmable Multi-Processor Architectures”, Microprocessing and Microprogramming, 41(5): 409-423, Oct. 1995.
De Greef, E., et al., “Memory Size Reduction Through Storage Order Optimization for Embedded Parallel Multimedia Applications”, International Parallel Processing Symposium (IPPS) in Proceedings Workshop on Parallel Processing and Multimedia, Geneva, Switzerland, pp. 84-98, Apr. 1997.
Diguet et al., “Formalized Methodology for Data Reuse Exploration in Hierarchical Memory Mappings”, International Symposium on Low Power Electronics and Design (IEEE Cat. No. 97TH8332), pp. 30-35, Aug. 1997.
Eles, P., et al., “Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems”, Proc. 1stACM/IEEE Design and Test in Europe Conf., Paris, France, pp. 132-128, Feb. 1998.
Fang, J., et al., “An Iteration Partition Approach for Cache or Local Memory Thrashing on Parallel Processing”, IEEE Transactions on Computers, vol. C-42, No. 5, pp. 529-546, May 1993.
Franssen et al., “Control Flow Optimization for Fast System Simulation and Storage Minimization”, European Design and Test Conference, 1994, pp. 20-24.
Ha, S., “Compile-Time Scheduling of Dynamic Constructs in Dataflow Program Graphs”, IEEE Trans. on Computers, vol. C-47, No. 7, pp. 768-778, Jul. 1997.
Hoang, P., “Scheduling of DSP Programs onto Multiprocessors for Maximum Throughput”, IEEE Trans. on Signal Processing, vol. 41, No. 6, Jun. 1993, pp. 2225-2235.
Hong, I., et al., On-Line Scheduling of Hard Real-Time Tasks on Variable Voltage, IEEE International Conf. on Comp. Aided Design, Santa Clara, CA, pp. 653-656, Nov. 1998.
Li, Y., et al., “Scheduling and Allocation on Single-Chip Multiprocessors for Multimedia”, IEEE Wsh. on Signal Processing Systems (SIPS), Leicester, UK, pp. 97-106, Nov. 1997, pp. 153-156.
Li, YanBing, et al., “A Task-Level Hierarchical Memory Model for System Synthesis of Multiprocessors”, Proceedings, 34thDesign Automation Conference, Jun. 1997.
Lippens, P., et al., “Allocation of Multiport Memories for Hierarchical Data Streams”, Proceedings IEEE International Conference on Computer Aided Designs, pp. 728-735, Santa Clara, Nov. 1993.
Marchal, P., et al., “Impact of task-level concurrency transformations on the MPEG4 IM1 player for weakly parallel processor platforms”, Wsh. on Compilers and Operating Systems for Low Power (COLP'00) in conjunction with Intnl. Conf. on Parallel Arch. And Compilation Techniques (PACT), Philadelphia, PA, Oct. 2000, 6 pages.
Marchal, P., et al., “Dynamic memory oriented transformations in the MPEG4 IM1-player on a low power platform”, Proc. Intnl. Wsh. On Power Aware Computing Systems (PACS), Cambridge, MA, pp. 31-40, Nov. 2000.
Moolenaar, et al., “System-Level Power Exploration for MPEG-2 Decoder on Embedded Cores: A Systematic Approach”, IEEE Workshop on Signal Processing Systems, 1997, pp. 395-404.
Nachtergaele, L., et al., “Optimization of Memory Organization and Hierarchy for Decreased Size and Power in Video and Image Processing Systems”, Proceedings International Workshop on Memory Technology, Design and Testing, San Jose, CA, pp. 82-87, Aug. 1995.
Nachtergaele L., et al., “Low Power Storage Exploration for H.263 Video Decoder, IEEE Workshop on VLSI Signal Processing”, Monterey, CA, pp. 114-124, Oct. 1996.
Pinter, S.S., “Register Allocation with Instruction Scheduling A New Approach”, ACM SIGPLAN Notices, vol. 28, pp. 248-257, Jun. 1993.
Prayati, A., et al., “Task concurrency management experiment for power-efficient speed-up of embedded MPEG4 IM1 player”, Proc. IEEE Conf. on Parallel Proc., Wsh. on Parallel and Distributed Multimedia Systems, Toronto, Canada, pp. 453-460, Aug. 2000.
Sentieys, O., et al., “Memory Module Selection For High Level Synthesis”, Proceedings IEEE Workshop on VLSI Signal Processing, Monterey, CA, pp. 272-283, Oct. 1996.
Slock, P., et al., “Fast and Extensive System-Level Memory Exploration for ATM Application” , Accepted for Proceedings 10thACM/IEEE International Symposium on System-Level Synthesis, Antwerp, Belgium, pp. 74-81, Sep. 1997.
Stok, L., “Data Path Synthesis”, The VLSI Journal, vol. 18, pp. 1-71, Jun. 1994.
Thoen, F., et al., “Modeling, Verification and Exploration of Task-Level Concurrency in Real-Time Embedded Systems”, ISBN 0-7923-7737-0, Kluwer Acad. Publ., Boston, 1999, no page numbers.
Tuck, B., “Raise your Sights to the System Level—Design Report 1997 Paris Forum”, Computer Design, pp. 53-74, Jun. 1997.
Verhaegh, W., et al., “Improved Force-Directed Scheduling in High-Throughput

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