Tapered dielectric etch in semiconductor devices

Details Tapered dielectric etch in semiconductor devices Tapered dielectric etch in semiconductor devices

1995-10-11

1998-03-17

Bowers, Jr., Charles L.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

438701, 438713, 438724, 438978, H01L 213065

Patent

active

057286086

ABSTRACT:
A method of etching openings in a dielectric layer of a semiconductor device by utilizing a novel etchant gas system of sulfur hexafluoride/chlorine such that sloped sidewalls can be formed in the openings having a desired taper of between about 20.degree. and about 85.degree. for achieving improved step coverage and profile control of the TFT fabrication process.

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patent: 5034339 (1991-07-01), Tanaka et al.
Translation of JP 61-248528.
Translation of JP 5-226654.
Translation of DE 3,714,144.
K. Fujii et al., Jpn. J. Appl. Phys. 31(I/12B)(Dec. 1992)4574 "Process . . . LCDs addressed by a-Si TFTs".
K. Tokashiki et al., Jpn. J. Appl. Phys. 30(I/11B)(Nov. 1991)3174 "Influence of halogen plasma atm. on SiO2 etching".
J. Pelletier et al., J. Vac. Sci. Technol. B7(1)(Jan. 1989)59 "Microwave plasma etching of Si and SiO2 in halogen . . . ".

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