TAP with control circuitry connected to device address port

Details TAP with control circuitry connected to device address port TAP with control circuitry connected to device address port

2009-03-10

2011-10-25

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S734000

Reexamination Certificate

active

08046650

ABSTRACT:
The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without the need for having a unique TMS signal for each device TAP in the arrangement. According to the disclosure, device TAPs are addressed by inputting an address on the TDI input of devices on the falling edge of TCK. An address circuit within the device is associated with the device's TAP and responds to the address input to either enable or disable access of the device's TAP.

REFERENCES:
patent: 6327681 (2001-12-01), Yamagishi et al.
patent: 7213185 (2007-05-01), Barone et al.
patent: 2006/0123306 (2006-06-01), Whetsel
Whetsel, L.; , “Inevitable use of TAP domains in SOCs,” Test Conference, 2002. Proceedings. International , vol., no., pp. 1191, 2002 doi: 10.1109/TEST.2002.1041898 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1041898&isnumber=22329.
Sehgal, A.; Ozev, S.; Chakrabarty, K.; , “Test infrastructure design for mixed-signal SOCs with wrapped analog cores,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol. 14, No. 3, pp. 292-304, Mar. 2006 doi: 10.1109/TVLSI.2006.871758 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1624378&isnumber=34100.

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