Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-04-20
2003-07-15
Everhart, Caridao (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S240000, C438S241000, C438S253000, C438S381000, C438S396000, C438S393000, C438S003000, C438S250000, C257S300000, C257S303000
Reexamination Certificate
active
06593181
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to insulating layers consisting of a mixture of crystalline and amorphous material states, and to devices that use such insulators. More specifically, this invention teaches a method for using ion implantation to amorphize insulators, thereby tailoring the insulator properties to optimize device performance. The invention also teaches the resulting mixed crystalline/amorphous perovskite materials, and the devices made with such materials.
BACKGROUND OF THE INVENTION
Insulating layers in the thickness range of 1 to 1000 nm have found wide use in integrated circuits. Almost all devices that make up today's integrated circuits, such as field effect transistors (FET), capacitors, decoupling capacitors, filters, and varactors, to name a few, are critically dependent on insulator properties. Also, one finds on a typical chip many non-device components with needs regarding dielectric properties of insulators that may be just as specific as those guiding the considerations for devices. Such might be the case for some passivation layers. When the circuits and the corresponding dielectrics are built on silicon wafers, the insulators of choice, almost universally, have been the oxides and nitrides of Si. These materials have relatively low dielectric constants, about 4 and 7 respectively. As circuits shrink and become more specialized, dielectrics with high dielectric constants (high k materials) also have become desirable alternatives. For instance, the need for high k materials is apparent for the case of the storage node of a DRAM cell. The cell needs high capacitance to store as much charge as possible, and there is a limit how thin the insulating layer can be made. Using a thin layer of SiO
2
as an example in a capacitor in a DRAM memory circuit, there is a limit to the minimum thickness that the SiO
2
can have. For example, at thicknesses below about 3 nm tunneling current starts to come into play, resulting in leaky capacitors, which are unable to store charge for sufficiently long times. The gate insulator in the FET's encounters similar limitations as miniaturization progresses. High k materials help miniaturization in general, since the area of any device can be made smaller if capacitance per unit area increases.
SUMMARY OF THE INVENTION
The object of the present invention is to overcome the deficiencies described, which result from the use of low dielectric constant insulating materials. The central idea of the present invention is to replace such materials by suitably tailored high k materials, and specifically how to achieve the exact desired value of dielectric constant with appropriate leakage current and stress/strain parameters.
If one can make use of a high k perovskite material, such as barium strontium titanate (BSTO), which can have a dielectric constant of about 300 at 30 nm thickness, one obtains high capacitance with low leakage due to the thickness of the film. Similar arguments are valid for many other capacitor dielectrics applications as well, where thicker films with less defects can be used when the dielectric constant is suitably high. However, often the properties of such high k dielectrics, apart of the high value of the dielectric, are not otherwise optimized for the intended use.
The as-deposition material structure of the typical perovskite is generally crystalline, almost exclusively polycrystalline. The object of this invention is to teach that after the manufacture of the device—incorporating the insulator—has already been essentially completed, one can in-situ controllably vary the dielectric constant of the insulator material. This is done by using ion implantation to convert the crystalline material of the insulator in part, or fully, to an amorphous material state. The amorphous material has a very different dielectric constant value than the crystalline material. A mixture of the crystalline and amorphous material exhibits a dielectric constant value which is in the range between the values of the fully crystalline and the fully amorphous material states. In this manner, depending on what fraction of the insulator is converted into the amorphous state, one can smoothly vary the dielectric constant of the final material from a value corresponding to the as deposited crystalline state, all the way to the dielectric value of the fully amorphous material. The parameters of the ion implanting, such as implant species, implant energy, implant dose, or possibly several species in combination at several energies and several doses, are chosen to achieve, or tailor, the insulator properties in a manner that the insulator properties match the operational requirements of the device.
It is important to emphasize the advantage that the conversion to amorphous material is done after the device manufacture is substantially completed. The dielectric at this stage is usually covered by a conducting electrode and possibly other layers commonly used in integrated circuit technology. Thus, for instance, in an array of capacitors if some, or even one of the capacitors has a very different value from the rest, it is possible to trim that capacitor even after the fabrication is complete.
It important as well, that while one is adjusting the dielectric constant by ion implantation, one can also get a lowering of the leakage current, and a relieving stress and strain at layer interfaces.
Different values of dielectric constant are needed for different applications. DRAM capacitors need the highest k for charge storage and the lowest leakage for charge retention. A 1 GBit DRAM will have 10
9
storage nodes with capacitors storing the charge at each node. Uniformity among the array is also desirable. FET gate dielectrics need not have such high dielectric constants and the leakage currents can be much higher. However, low leakage is also desirable for FETS, particularly for portable applications. Filters, decoupling capacitors, and varactors need to have dielectric values somewhere in between the values used for DRAMS and for gates. Thus, in modern integrated circuitry applications, it will be necessary to have available for circuit designers materials in thin layer form whose dielectric constant can be controllably varied.
In another embodiment the possibility to vary the dielectric constant of an insulator in a broad range, with the spatial precision of ion implantation, lends itself for use in optical devices, such as dielectric mirrors, filters and gratings.
We have shown that the electrical properties of perovskite materials in thin film form can be controllably altered by amorphizing the material with such implant species as Cr, Cl, Ti, Mn, and Nb. Also lighter ion species like F, H and D have their useful points, such as deeper penetration at lower energies.
Typical perovskite materials for use in this invention include strontium titanate (STO), barium titanate(BTO), and the compound barium strontium titanate (BSTO). Similar materials of use include lead titanate, lead bismuth titanate, strontium bismuth titanate and those materials in which Nb and Ta atoms substitute for the titanium atom. Typically the perovskite formula is ABO where for the case of STO A═Sr, B═Ti and O═O. While for BSTO, A=a combination of Ba and Sr, typically given by a ratio x whereby A═Ba(1−x)Sr(x). In the experimental descriptions that follow BSTO is used as the prime embodiment, with x=0.3
The as deposited thin layers of perovskite materials are either fully crystalline or fully amorphous. Which of the two states one ends up with depends on the mode of deposition, and importantly, on the temperature. One obtains as deposited amorphous material only at low temperatures, typically below few hundred degrees C. The perovskite layers that one deposits during the fabrication process of integrated circuits, where temperatures range in the 1000° C., are crystalline. Consequently the mixed crystalline/amorphous perovskite layers in integrated circuits are novel materials by themselves. The devi
Baniecki John David
Bednorz Johannes Georg
Laibowitz Robert Benjamin
Locquet Jean-Pierre A.
Everhart Caridao
Keshavan Belur V
Sai-Halasz George
Trepp Robert M.
LandOfFree
Tailored insulator properties for devices does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Tailored insulator properties for devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Tailored insulator properties for devices will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3097240