Tagged address stack and microprocessor using same

Details Tagged address stack and microprocessor using same Tagged address stack and microprocessor using same

2005-03-01

2005-03-01

Nguyen, T (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S117000, C711S118000, C711S132000, C711S133000

Reexamination Certificate

active

06862670

ABSTRACT:
A tag address stack (TAS) for reducing the number of address latches and address comparators needed to insure data coherency in a pipelined microprocessor. The TAS is a small pool of address latches shared among data buffers in the microprocessor that stores a unique set of memory addresses that specify data in the data buffers. A correspondingly small number of address comparators compare the unique TAS addresses with a new load/store address. If the new address matches a TAS address, the new load/store operation latches a unique tag associated with the matching TAS address. Otherwise, the new address is loaded into a free latch and the new load/store latches its associated unique tag. If no latches are free, the pipeline stalls until a latch in the pool becomes free. Rather than storing the full addresses in conjunction with the data buffers, the tags are stored, which facilitates faster compares.

REFERENCES:
patent: 5584003 (1996-12-01), Yamaguchi et al.
patent: 5740416 (1998-04-01), McMahan
patent: 5835967 (1998-11-01), McMahan
patent: 5987561 (1999-11-01), Witt et al.
patent: 6021471 (2000-02-01), Stiles et al.
patent: 6594728 (2003-07-01), Yeager

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