Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2007-07-17
2007-07-17
Elmore, Stephen C. (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S100000, C711S101000, C711S170000, C710S003000, C710S036000, C710S038000, C365S189011, C365S230030
Reexamination Certificate
active
10721178
ABSTRACT:
A short latency and high bandwidth memory includes a systolic memory that is sub-divided into a plurality of memory arrays, including banks and pipelines that access these banks. Shorter latency and faster performance is achieved with this memory, because each bank is smaller in size and is accessed more rapidly. A high throughput rate is accomplished because of the pipelining. Memory is accessed at the pipeline frequency with the proposed read and write mechanism. Design complexity is reduced because each bank within the memory is the same and repeated. The memory array size is re-configured and organized to fit within desired size and area parameters.
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Lu Shih-Lien L.
Somasekhar Dinesh
Ye Yibin
Elmore Stephen C.
Ked & Associates LLP
Kim Daniel
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