Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-10-09
2007-10-09
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C324S606000
Reexamination Certificate
active
11168033
ABSTRACT:
In one embodiment, an automated circuit test system is calibrated by electrically coupling a first calibration unit between a plurality of drivers and comparators of the test system, and then executing an AC timing calibration procedure to determine a timing delay for each of a first set of relationships. A second calibration unit is then electrically coupled between the plurality of drivers and comparators, and an AC timing calibration procedure is executed to determine a timing delay for each of a second set of relationships. The first and second calibration units comprise fixed wiring paths that respectively couple pairs of the drivers and comparators in accord with the first and second sets of relationships. A set of equations is solved based on the timing delays and driver/comparator relationships to determine relative timing errors introduced by signal paths of the test system including the drivers and comparators.
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“Adaptive enhancement of timing accuracy and waveform quality inhigh-performance IC testers” Charoen et al. This paper appears in: Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on Publication Date: Feb. 1992 vol. 39, Issue: 2 On pp. 139-151ISSN: 1057-7122 INSPEC Accession No. 4135755.
Britt Cynthia
Verigy (Singapore Pte. Ltd.
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