Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2004-05-07
2008-08-26
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07418684
ABSTRACT:
A method and an apparatus to perform static timing analysis and optimization for multi-mode clock circuit networks have been disclosed. In one embodiment, the method includes determining a plurality of sensitization conditions associated with one or more clock signals in a circuit network operable in a plurality of modes and automatically eliminating false paths from a plurality of clock paths of the circuit network based on the plurality of sensitization conditions. Other embodiments have been claimed and described.
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Kriplani Harish
Moon Cho W.
Alford William E.
Alford Law Group, Inc.
Cadence Design Systems Inc.
Dinh Paul
Wong Teresa
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