Systems, methods, and apparatus to perform static timing...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000

Reexamination Certificate

active

07418684

ABSTRACT:
A method and an apparatus to perform static timing analysis and optimization for multi-mode clock circuit networks have been disclosed. In one embodiment, the method includes determining a plurality of sensitization conditions associated with one or more clock signals in a circuit network operable in a plurality of modes and automatically eliminating false paths from a plurality of clock paths of the circuit network based on the plurality of sensitization conditions. Other embodiments have been claimed and described.

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Cherry, James J., Pearl: A CMOS Timing Analyzer, Design Automation Conference, pp. 148-159, 1998.

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