Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2011-02-08
2011-02-08
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
07886242
ABSTRACT:
In some embodiments of the invention, a method and apparatus of consolidating all types of coverage metrics, obtained from an HDL simulator, under a single common framework is described. In other embodiments of the invention, a method and an apparatus are disclosed for performing ranking from a verification plan using total coverage metric.
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Chakraborti Swapnajit
Duek-Golan Yael
Gommershtadt Boris
Pagey Sandeep
Alford William E.
Alford Law Group, Inc.
Cadence Design Systems Inc.
Chiang Jack
Parihar Suchin
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