Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2011-03-22
2011-03-22
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S124000
Reexamination Certificate
active
07913194
ABSTRACT:
In one embodiment of the invention, a method is disclosed including receiving a netlist of an integrated circuit design; executing a first copy of an integrated circuit design program with a first processor associated with a first memory space to independently perform work on a first portion of the integrated circuit design; and executing a second copy of the integrated circuit design program with a second processor associated with a second memory space to independently perform work on a second portion of the integrated circuit design; wherein the second memory space is independent of the first memory space.
REFERENCES:
patent: 5928369 (1999-07-01), Keyser et al.
patent: 6662358 (2003-12-01), Berry et al.
patent: 6857110 (2005-02-01), Rupp et al.
patent: 2002/0080174 (2002-06-01), Kodosky et al.
patent: 2006/0053396 (2006-03-01), Eng
Alford William E.
Alford Law Group, Inc.
Cadence Design Systems Inc.
Chiang Jack
Tat Binh C
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