Systems and methods for simultaneously testing semiconductor...

Details Systems and methods for simultaneously testing semiconductor... Systems and methods for simultaneously testing semiconductor...

2004-04-13

2009-06-23

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S719000

Reexamination Certificate

active

07552368

ABSTRACT:
A method for testing a memory cell array of a semiconductor memory device in a parallel bit test mode includes selecting first data from one of a plurality of memory regions in the memory array for output from the memory device via an input/output pad, and then selecting second data from another of the plurality of memory regions for output via the input/output pad. The first and second data can be selected from memory regions sharing a row select or a column select control line. Alternatively, one of the first and second data can be selected from memory regions sharing a row select control line, and the other can be selected from memory regions sharing a column select control line. Therefore, a parallel bit test can be performed using fewer input/output pads, and a larger number of semiconductor memory devices can simultaneously be tested. Related circuits are also discussed.

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Korean Office Action corresponding to Korean Application No. 10-2003-0038890 dated Apr. 18, 2005.

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