Systems and methods for signature circuits

Details Systems and methods for signature circuits Systems and methods for signature circuits

2005-04-01

2008-10-14

Chaudry, Mujtaba K (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S758000, C714S742000

Reexamination Certificate

active

07437641

ABSTRACT:
Signature circuits are used during testing of an integrated circuit. Test vectors are applied as inputs to a circuit under test. A signature circuit stores a “signature” for the circuit under test based on a combination of signals from the circuit under test in response to test vectors and a previous stored state of the signature register. The value contained in the signature register at the end of the test is the signature. A fault-free circuit generates a particular signature for the applied test vectors. Faults can be determined by detecting variances from the expected signature. In one embodiment, the signature circuit uses a combination of two error detection codes.

REFERENCES:
patent: 5938784 (1999-08-01), Kim
patent: 5960009 (1999-09-01), Gizopoulos
patent: 6247154 (2001-06-01), Bushnell et al.
patent: 6681357 (2004-01-01), Pendurkar
patent: 6701476 (2004-03-01), Pouya et al.
patent: 6715105 (2004-03-01), Rearick
patent: 6920604 (2005-07-01), Coakeley et al.
patent: 2002/0184582 (2002-12-01), Pouya et al.
patent: 2002/0184586 (2002-12-01), Pendurkar
patent: 2006/0179393 (2006-08-01), Harter et al.
patent: 2007/0245133 (2007-10-01), Weiberle et al.
patent: 2002-243805 (2002-08-01), None
Abramovici, M et al., “Digital Systems Testing And Testable Design,” 1990, Computer Science Press, New York, pp. 421-449.
Hayes, J. P., “Check Sum Test Methods,” Proceedings of Fault Tolerant Computing Symposium, 1976, pp. 114-120.
Chandra, A., et al., “Systems-on-a-Chip Test-Data Compression and Decompression Architectures Based on Golomb Codes,” IEEE Transactions on Computer-Aided Design, Mar. 2001, pp. 355-368, vol. 20, No. 3.
Chakrabarty, K., et al., “Test Response Compaction Using Multiplexed Parity Trees,” IEEE Transactions on Computer-Aided Design, Nov. 1996, pp. 1399-1408, vol. 15, No. 11.
Reddy, S.M., et al., “A Data Compression Technique for Built-In Self Test,” IEEE Transactions on Computers, Sep. 1998, pp. 1151-1156, vol. 37, No. 9.
Chakrabarty, K., et al., “Optimal Space Compaction of Test Responses,” Proceedings of International Test Conference, 1995, pp. 834-843.
Saxena, N., et al., “Syndrome and Transition Count are Uncorrelated,” IEEE Transactions on Information Theory, Jan. 1988, pp. 64-69, vol. 34, No. 1.
Robinson, J., et al. “Simultaneous Signature and Syndrome Compression,” IEEE Transactions on Computer-Aided Design, May 1988, pp. 584-589, vol. 7, No. 5.

Affiliated with

Also associated with

Rating

Systems and methods for signature circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Systems and methods for signature circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Systems and methods for signature circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4015079