Electrical computers and digital data processing systems: input/ – Input/output data processing – Concurrent input/output processing and data transfer
Reexamination Certificate
1997-04-18
2002-07-23
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Concurrent input/output processing and data transfer
C710S004000, C710S120000
Reexamination Certificate
active
06425020
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates in general to information processing systems and in particular to passive data transfer circuits, systems and methods.
BACKGROUND OF THE INVENTION
Often times in computing environments, data must be transferred from one memory location to another. These transfers can either be between separate memory subsystems (devices) across an external data bus or internally within the same memory subsystem (device). Transfers between separate memory subsystems occur for example when data are transferred from the system memory to the frame buffer during display data update. A typical example when transfers are performed within the same memory subsystem is during the movement of bit-mapped display data between locations within the frame buffer to effectuate the movement of a “window” of data on the display screen.
A common method of transferring data between subsystems is “bus mastering.” In a bus mastering system, a bus controller resides within the core logic and a bus master resides with each subsystem on the bus, for example within the display controller of the display controller-frame buffer subsystem. For discussion, assume that the display subsystem requires data from the system memory. Then, the display controller bus master sends a request to the bus controller for access to the bus and consequently the system memory. The bus controller arbitrates the request with any other requests pending and when able, sends a grant to the requesting bus master, in this case within the display controller. The display controller bus master then controls the bus to the exclusion of all other subsystems, including the CPU.
The full advantages of bus mastering are typically only achieved during the transfers of substantial amounts of data, which are not frequently necessary in the personal computer (PC) environment. Among other things, bus mastering is logic intensive and significantly increases operating overhead. In addition to the logic required to control data flow, the bus master must also include the timing logic necessary to insure that the bus is relinquished before a system crash occurs, since typically even the CPU cannot override the active bus master.
Bit block transfer (“Bit BLT” or simply “BLT”) engines are often used when blocks of are transferred from one set of memory locations to another. A bit block transfer can be performed between subsystems, such as between the system memory and the frame buffer, or within a subsystem, such as within the frame buffer. For example, a bit block transfer is commonly used when data is moved from one position on the display screen to another, such as when a window is “dragged” across the screen by a mouse. In this case, the bit block engine (circuitry and software) moves the corresponding bitmapped pixel data in the frame buffer (display memory) from the address space corresponding to the original display position to the address space corresponding to the new display position. Similarly, entire blocks of data may be copied from a set of source locations in memory to a set of destination locations in memory by a block copy.
There are a number of known techniques for implementing bit block transfers (copies). For example, a block of source locations in memory may be identified by the addresses corresponding to a pair of “corners” of the block, the address of one “corner” defining a starting row and a starting column address, and the address of a second corner defining an ending row and an ending column address. Alternatively, a block of storage locations being moved or copied can be defined by a single starting address (“corner”) and a block size (“dimensions”)from which the ending address can be defined. In either case, once the starting and ending addresses for the source block are defined, the remaining source addresses can be derived therefrom using counters and associated circuitry. Similarly, a block of destination addresses are defined. Data is then transferred between the source and destination blocks by incrementing the source and destination addresses and presenting the appropriate read and write commands.
Bit block transfers also have disadvantages. In particular, bit block transfers are inherently speed-limited. Essentially, during a bit block transfer, data are read from the source block of memory a word or byte at a time and correspondingly written into the destination block of memory a word or byte at a time. This “streaming” of data is time consuming and requires a substantial amount of controller and/or bus bandwidth.
It should also be noted that data transfers between locations within a subsystem or between subsystems can be controlled by the CPU itself. This is typically the case when bus mastering is not used. However, these transfers consume valuable CPU time otherwise available to perform other tasks and are often subject to latency problems. For example, two cycles are required, a first for reading the data from the source location and a second for writing data into the destination location.
Thus, the need has arisen for new circuits, systems and methods for performing data transfers. Such circuits, systems and methods should apply to either inter- and intra-subsystem transfers and provide speed increases and overhead reductions over the prior art.
SUMMARY OF THE INVENTION
According to a first embodiment of the present invention, processing circuitry is disclosed having passive data transfer capability. The processing circuitry includes a bus, a first subsystem coupled to the bus through first passive transfer logic, and a second subsystem coupled to the bus through second passive transfer logic. Control circuitry is coupled to the bus for initiating a passive data transfer between the first and second subsystems, the first and second passive transfer logic thereafter controlling exchange of data between the first and second subsystems independent of the control circuitry.
According to a second embodiment of the principles of the present invention, a processing system is disclosed which includes a bus, passive transfer circuitry coupled to the bus and control circuitry. The control circuitry is operable during a configuration cycle to configure the passive transfer circuitry to transfer data across the bus during a transfer cycle, the transfer of data during a transfer cycle being performed by the passive transfer circuitry independent of the control circuitry.
The principles of the present invention are also embodied in methods of passively transferring data in information processing systems. According to one such method, passive data transfer capability is provided in a system including a plurality of data processing resources each coupled to a bus through associated passive transfer logic. One of the plurality of resources is selected as the source resource. Configuration information is transmitted on the bus configuring the passive transfer logic associated with the source resource to transfer data from the source resource to a selected destination resource. Data is then transmitted from the source resource via the passive transfer logic associated with the source resource to the passive transfer logic associated with a destination resource via the bus.
According to a second such method, a selected one of a plurality of resources is selected as the destination resource. Configuration information is transmitted on a bus configuring the passive transfer logic associated with the destination resource to exchange data with the bus. Data is then transmitted on the bus for exchange with the destination resource through the passive transfer logic associated with the destination resource.
The principles of the present invention provide substantial advantages over the prior art. Among other things, these principles, as embodied in circuits, systems and methods, provide for either inter- or intra-subsystem transfers of data with increased speed and reduced overhead.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in
Cirrus Logic Inc.
Du Thuan
Lee Thomas
Murphy James J.
Winstead SEchrest & Minick
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