Systems and methods for implementing inter-device cell replaceme

Static information storage and retrieval – Read/write circuit – Bad bit

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Details

3652257, 36523003, G11C 700

Patent

active

056572816

ABSTRACT:
A memory system 200 including a first memory unit 201 having an array of memory cells and a second memory unit 201 having an array of memory cells including a number of redundant cells. A crossbar switch 202 is provided for switching an address to a defective cell in the array of the first memory unit 201 to the second memory unit 202 to access a selected one of the redundant cells.

REFERENCES:
patent: 5265054 (1993-11-01), McClure
patent: 5381370 (1995-01-01), Lacey et al.
patent: 5485424 (1996-01-01), Kawamura
patent: 5523974 (1996-06-01), Hirano et al.

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