Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Signal level or switching threshold stabilization
Reexamination Certificate
2011-07-19
2011-07-19
Le, Don P (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Signal level or switching threshold stabilization
C326S026000
Reexamination Certificate
active
07982494
ABSTRACT:
Embodiments of the present invention include systems for calibrating an output circuit. A comparator is coupled to a calibration terminal and configured to determine whether the calibration terminal is in a first state coupled to a calibration resistor or in a second state. A calibration circuit is coupled to the calibration terminal and configured to generate a calibration value based in part on the presence or absence of the calibration resistor. An impedance selector is coupled to the calibration circuit, the comparator, and a default calibration value. The impedance selector is configured to select the default calibration value when the comparator indicates the calibration terminal is in the second state and to select the calibration value coupled from the calibration circuit when the comparator indicates the calibration terminal is in the first state.
REFERENCES:
patent: 6031385 (2000-02-01), Ilkbahar
patent: 6262625 (2001-07-01), Perner et al.
patent: 6807650 (2004-10-01), Lamb et al.
patent: 6836143 (2004-12-01), Song
patent: 6839286 (2005-01-01), Cho et al.
patent: 6947336 (2005-09-01), Kim et al.
patent: 6958613 (2005-10-01), Braun et al.
patent: 7514954 (2009-04-01), Kim et al.
patent: 7535250 (2009-05-01), Batt
patent: 7573288 (2009-08-01), Ayyapureddi et al.
patent: 7804324 (2010-09-01), Ayyapureddi et al.
patent: 2002/0063576 (2002-05-01), Kim et al.
patent: 2003/0218914 (2003-11-01), Kim et al.
patent: 2007/0040573 (2007-02-01), Batt
patent: 2007/0200591 (2007-08-01), Kim
patent: 2007/0263459 (2007-11-01), Kim et al.
patent: 2009/0146685 (2009-06-01), Kim et al.
patent: 2009/0273364 (2009-11-01), Jeong et al.
patent: 2009/0295426 (2009-12-01), Ayyapureddi et al.
Todd Farrell; “Core Architecture Doubles Mem Data Rate”; EE Times Asia; Dec. 16, 2005; EE Times Asia; eMedia Asia Ltd.; New York, NY; http://www.eetasia.com/MUL—technical-articles—32—TA.HTM.
Graham Allan; “The Outlook for DRAMs in Consumer Electronics”; EDA Tech Forum; Jan. 12, 2007; CMP Media LLP; Manhasset, NY; http://edadesignline.com/196900432;jsessionis—IP1AF51SS4QEEQSNDLPCKHSCJUNN2JVN?printableArticle—true.
Blodgett Greg
Sreeramaneni Raghu
Vankayala Vijay
Dorsey & Whitney LLP
Le Don P
Micro)n Technology, Inc.
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