Systems and methods for data transfers between memory cells

Details Systems and methods for data transfers between memory cells Systems and methods for data transfers between memory cells

2008-02-19

2010-10-05

Mai, Son L (Department: 2827)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S189011, C365S190000

Reexamination Certificate

active

07808854

ABSTRACT:
Systems and methods for reducing the latency of data transfers between memory cells by enabling data to be transferred directly between sense amplifiers in the memory system. In one embodiment, a memory system uses a conventional DRAM memory structure having a pair of first-level sense amplifiers, a second-level sense amplifier and control logic for the sense amplifiers. Each of the sense amplifiers is configured to be selectively coupled to a data line. In a direct data transfer mode, the control logic generates control signals that cause the sense amplifiers to transfer data from a first one of the first-level sense amplifiers (a source sense amplifier) to the second-level sense amplifier, and from there to a second one of the first-level sense amplifiers (a destination sense amplifier.) The structure of these sense amplifiers is conventional, and the operation of the system is enabled by modified control logic.

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