Systems and methods for adaptively mapping an instruction cache

Details Systems and methods for adaptively mapping an instruction cache Systems and methods for adaptively mapping an instruction cache

2005-03-02

2008-12-23

Sough, Hyung (Department: 2188)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S206000, C711S125000

Reexamination Certificate

active

07469332

ABSTRACT:
Systems and methods for adaptively mapping system memory address bits into an instruction tag and an index into the cache are disclosed. More particularly, hardware and software are disclosed for observing collisions that occur for a given mapping of system memory bits into a tag and an index. Based on the observations, an optimal mapping may be determined that minimizes collisions.

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patent: 0 674 268 (1995-09-01), None
Gideon Intrater, et al., “Performance Evaluation of a Decoded Instruction Cache for Variable Instruction-Length Computers,” 1992 ACM, pp. 106-113.

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