Systems and methods for a high density, compact memory array

Details Systems and methods for a high density, compact memory array Systems and methods for a high density, compact memory array

2006-01-06

2009-10-27

Jackson, Jr., Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE21679, C257SE29309

Reexamination Certificate

active

07608886

ABSTRACT:
A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi level charge techniques can be used to increase the number of bit per cell and achieve further increased density for the memory array.

REFERENCES:
patent: 5049956 (1991-09-01), Yoshida et al.
patent: 5973356 (1999-10-01), Noble et al.
patent: 6143636 (2000-11-01), Forbes et al.
patent: 6486028 (2002-11-01), Chang et al.
patent: 7301804 (2007-11-01), Prall et al.
patent: 2004/0066672 (2004-04-01), Forbes

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