System verification using one or more automata

Details System verification using one or more automata System verification using one or more automata

2007-10-30

2007-10-30

Kerveros, James C. (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S741000

Reexamination Certificate

active

10957259

ABSTRACT:
A method and apparatus for manipulating a non-deterministic automaton and a traversal of a non-deterministic automaton for dynamic verification of a system or device under test is described herein.

REFERENCES:
patent: 6226716 (2001-05-01), Bauman et al.
patent: 6385750 (2002-05-01), Kapur et al.
patent: 6707313 (2004-03-01), Rohrbaugh et al.
patent: 2002/0124208 (2002-09-01), Beer et al.
patent: 2003/0159132 (2003-08-01), Barnett et al.
patent: 2004/0019839 (2004-01-01), Krech et al.
patent: 2006/0047461 (2006-03-01), Sivaram et al.
Aharon, et al., “Verification of the IBM RISC System/6000 by a dynamic biased pseudo-random test program generator”, IBM Systems Journal, vol. 30, No. 4, pp. 527-538, 1991.
Aharon, et al., “Test Program Generation for Functional Simulation of PowerPC Processors in IBM”, Proceedings of the IEEE/ACM Design Automation Conference, pp. 279-285, 1995.
Ahi, et al., “Design Verification of the HP 9000 Series 700 PA0RISC workstations”, Hewlett-Packard Journal, vol. 43, No. 4, pp. 34-42, Aug. 1992.
Aho, et al., “An Optimization Technique for Protocol Conformance Test Generation Based on UIO Sequences and Rural Chinese Postman Tours”, IEEE Transactions on Communications, vol. 39, No. 11, pp. 1604-1615, 1991.
Alexander, et al., “Verification, Characterization, and Debugging of the HP PA 7200 Processor”, Hewlett-Packard Journal, vol. 47, No. 1, article 4, Feb. 1996.
Anderson, Walker, “Logical Verification of the NVAX CPU Chip Design”, Proceedings of the 1991 IEEE International Conference on Computer Design of VLSI in computer & Processors, pp. 306-309.
Apfelbaum, Larry, “Automated Functional Test Generation”, Proceedings of the Autotestcon '95 Conference, pp. 101-107, 1995.
Apfelbaum, Larry, “Spec-based tests make sure telecom software works”, IEEE Spectrum, Nov. 1997.
Balcer, et al., “Automatic Generation of Test Scripts from Formal Test Specifications”, Proceedings of the ACM SIGSOFT '89 3rdSymposium on Software Testing, Analysis, and Verification, pp. 210-218, 1989.
Bazzichi, et al., “An Automatic Generator for Compiler Testing”, IEEE Transactions on Software Engineering, vol. SE-8, No. 4, pp. 343-353, Jul. 1982.
Bellon, et al., “Automatic Generation of Microprocessor Test Programs”, Proceedings of the IEEE/ACM 19thDesign Automation Conference, pp. 566-573, 1982.
Bird, et al., “Automatic generation of random self-checking test cases”, IBM Systems Journal, vol. 22, No. 3, 1983.
Chandra, et al., “Architectural Verification of Processors Using Symbolic Instruction Graphs”, Proceedings of International Conference on Computer Design, pp. 454-459, Oct. 1994.
Chandra, et al., “AVPGEN—A Test Generator for Architecture Verification”, IEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 3, No. 2, pp. 188-200, Jun. 1996.
Chandrasekharan, et al., “Requirements-Based Testing of Real-Time Systems: Modeling for Testability”, IEEE Computer, pp. 71-80, Apr. 1985.
Chanson, et al., “A Unified Approach to Protocol Test Sequence Generation”, Proceedings of IEE INFOCOM-93, vol. 1, pp. 106-114, Mar. 1993.
Cheng, et al., “Automatic Functional Test Generation Using the Extended Finite State Machine Model”, Proceedings of the IEE/ACM 30thDesign Automation Conference, pp. 86-91, 1993.
DeMillo, et al., “Constraint-Based Automatic Test Data Generation”, IEEE Transactions on Software Engineering, vol. 17, No. 9, Sep. 1991.
DeMillo, et al., “Experimental Results from an Automatic Test Case Generator”, ACM Transactions on Software Engineering and Methodology, vol. 2, No. 2, Apr. 1993.
Deng, et al., “Exploring an Unknown Graph (Extended Abstract)”, Proceedings of the 31stAnnual IEEE Symposium on Foundations of Computer Science, pp. 355-362, 1990.
Diep, et al., “Systematic Validation of Pipeline Interlock for Superscalar Microarchitectures”, Proceedings of the 25thAnnual Symposium on Fault-Tolerant Computing, pp. 100-109, 1995.
Duncan, et al., “Using Attributed Grammars to test Designs and Implementations”, Proceedings of the 5thInternational Conference on Software Engineering, pp. 170-178, 1981.
Dushina, et al., “Semi-Formal Test Generation with Genevieve”, Proceedings of the IEEE/ACM 38thDesign Automation Conference, pp. 617-622, 2001.
Frankl, et al., “Provable Improvements on Branch Testing”, IEEE Transactions on Software Engineering, vol. 19, No. 10, Oct. 1993.
Gronau, et al., “A Methodology and Architecture for Automated Software Testing”, Technical Report, IBM Research Laboratory in Haifa, Israel, 2000.
Hanford, K.V., “Automatic Generation of Test Cases”, IBM Systems Journal, vol. 9, No. 4, pp. 242-257, 1970.
Harm, et al., “Testing Attribute Grammars”, Proceedings of the 3rdWorkshop on Attribute Grammars and their Applications (WAGA2000), pp. 79-98, Jul. 2000.
Hayes, et al., “Increased Software Reliability Through Input Validation Analysis and Testing”, Proceedings of the 10thIEEE International Symposium on Software Reliability Engineering (ISSRE '99), pp. 199-209, Nov. 1999.
Homer, et al., “Independent Testing of Compiler Phases Using a Test Case Generator”, Software-Practice and Experience, vol. 19, No. 1, p. 53-62, Jan. 1989.
Ho, et al., “Architecture Validation for Processors”, Proceedings of the International Symposium on Computer Architecture, pp. 404-413, 1995.
Hopcroft, et al., Introduction to Automata Theory, Languages, and Computation, pp. 19-35, ISBN 0-201-02988-X, Addison-Wesley Publishing Company, Inc., 1979.
Horgan, et al., A Data Flow Coverage Testing Tool for “C”, Proceedings of the Symposium on Assessment of Quality Software Development Tools, pp. 2-10, May 1992.
Iwashita, et al., “Behavioral Design and Test Assistance for Pipelined Processors”, Proceedings of the IEEE 1stAsian Test Symposium, pp. 8-13, 1992.
Iwashita, et al., “Automatic Program Generator for Simulation-Based Processor Verification”, Proceedings of the IEEE 3rdAsian Test Symposium, pp. 298-303, 1994.
Kantrowitz, et al., “Functional Verification of a Multiple-Issue, Pipelined, Superscalar Alpha Processor—the Alpha 21164 CPU Chip”, Digital Technical Journal, vol. 7, No. 1, pp. 136-144, Jan. 1996.
Kantrowitz, et al., “I'm Done Simulating; Now What? Verification Coverage Analysis and Correctness Checking of the DECchip 21164 Alpha Microprocessor”, Proceedings of the 33rdIEEE/ACM Design Automation Conference, pp. 325-330, 1996.
Klug, Hans-Peter, “Microprocessor Testing by Instruction Sequences Derived from Random Patterns”, Proceedings of the International Test Conference, pp. 73-80, 1988.
Lee, et al., “Functional Test Generation for Pipelined Computer Implementations”, Proceedings of the 21stAnnual International Symposium on Fault-Tolerant Computering, pp. 60-67, 1991.
Lee, et al., “Conformance Testing of Protocols Specified as Communicating FSMs”, Proceedings of IEE INFOCOM-93, pp. 115-127, Mar. 1993.
Lee, et al., “Principles and Methods of Testing Finite State Machines—A Survey”, Proceedings of the IEEE, vol. 84, No. 8, Aug. 1996.
Lichtenstein, et al., “Model Based Test Generation for Processor Verification”, Proceedings of the 6thInnovative Applications of Artificial Intelligence Conference (IAAI-94), pp. 83-94, Aug. 1994.
Logan, Carol A., “Directions in Multiprocessor Verification”, Proceedings of the 14thAnnual International Phoenix Conference on Computers and Communications, pp. 25-33, Jun. 1995.
Lin, et al., “Automatic Functional Test Program Generation for Microprocessors”, Proceedings of the 25thIEEE/ACM Design Automation Conference, pp. 605-608, 1988.
Malloy, et al., “A

Affiliated with

Also associated with

Rating

System verification using one or more automata does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System verification using one or more automata, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System verification using one or more automata will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3871902