System to reduce programmable range specifications for a...

Details System to reduce programmable range specifications for a... System to reduce programmable range specifications for a...

2007-04-04

2010-02-09

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S740000, C714S047300, C714S709000, C714S721000, C714S742000, C714S745000, C365S201000, C326S030000, C327S156000, C327S158000, C331S1170FE, C702S107000

Reexamination Certificate

active

07661051

ABSTRACT:
An apparatus comprising a comparator circuit, a reference circuit, a plurality of elements and a logic circuit. The comparator circuit may be configured to generate a difference signal in response to (i) a reference signal and (ii) a test signal. The reference circuit configured to generate the reference signal in response to a first control signal. The plurality of elements may each be configured to generate an intermediate test signal. One of the intermediate test signals may be presented as the test signal by activating one of the test elements, in response to a second control signal. The logic circuit may be configured to generate (i) the first control signal and (ii) the second control signal, each in response to the difference signal.

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